Calibration circuit, semiconductor device including the same, and method of adjusting output characteristics of semiconductor device
View Patent ↗A calibration circuit includes: a replica buffer that drives a calibration terminal ZQ; a reference voltage generating circuit that generates a reference voltage VMID; a comparing circuit that compares a voltage appearing in the calibration terminal ZQ with the reference voltage VMID; an impedance adjusting circuit that changes an output impedance of the replica buffer based on a result of comparison carried out by the comparing circuit; and a reference voltage adjusting circuit that adjusts the reference voltage VMID. With this arrangement, the reference voltage VMID can be offset by taking into account a resistance component present between the calibration terminal ZQ and the external terminal, and therefore, a more accurate calibration operation can be carried out.
1. A semiconductor device comprising:
first replica buffer coupled to a first calibration terminal;
second replica buffer coupled to a second calibration terminal;
third replica buffer coupled to the second calibration terminal;
first reference voltage generating circuit generating a first reference voltage that is subject to be adjustable;
second reference voltage generating circuit generating a second reference voltage that is fixed;
first comparing circuit comparing a voltage of the first calibration terminal with the first reference voltage to control impedance of the first and second replica buffers; and
a second comparing circuit comparing a voltage of the second calibration terminal with the second reference voltage to control an impedance of the third replica buffer.
2. The semiconductor device as claimed in claim 1 , wherein the first reference voltage generating circuit includes a selector that selects the first reference voltage from one or more voltages of which potentials are different from each other, and includes a nonvolatile memory element.
3. The semiconductor device as claimed in claim 2 , wherein the nonvolatile memory element is an electrically writable element.
4. The semiconductor device as claimed in claim 3 , wherein the nonvolatile memory element is an antifuse.
5. The semiconductor device as claimed in claim 1 , wherein the first reference voltage generating circuit includes a high-resistance part and a low-resistance part, and one or more voltages are taken out from the low-resistance part.
6. The semiconductor device as claimed in claim 5 , wherein the high-resistance part includes a diffusion-layer resistor, and the low-resistance part includes a wiring resistor.
7. The semiconductor device as claimed in claim 1 , wherein the first replica buffer has one of a pull-up function and a pull-down function, and the third replica buffer has the other of the pull-up function and a pull-down function.
8. A semiconductor device comprising:
a first replica buffer coupled to a first calibration terminal;
a second replica buffer coupled to a second calibration terminal;
a third replica buffer coupled to the second calibration terminal;
a first reference voltage generating circuit generating a first reference voltage;
a second reference voltage generating circuit generating a second reference voltage that is substantially different from the first reference voltage;
a first comparing circuit comparing a voltage of the first calibration terminal with the first reference voltage to control impedance of the first and second replica buffers; and
a second comparing circuit comparing a voltage of the second calibration terminal with the second reference voltage to control an impedance of the third replica buffer.
9. The semiconductor device as claimed in claim 8 , wherein the first reference voltage generating circuit includes a selector that selects the first reference voltage from one or more voltages of which potentials are different from each other, and includes a nonvolatile memory element.
10. The semiconductor device as claimed in claim 9 , wherein the nonvolatile memory element is an electrically writable element.
11. The semiconductor device as claimed in claim 10 , wherein the nonvolatile memory element is an antifuse.
12. The semiconductor device as claimed in claim 8 , wherein the first reference voltage generating circuit includes a high-resistance part and a low-resistance part, and one or more voltages are taken out from the low-resistance part.
13. The semiconductor device as claimed in claim 12 , wherein the high-resistance part includes a diffusion-layer resistor, and the low-resistance part includes a wiring resistor.
14. The semiconductor device as claimed in claim 8 , wherein the first replica buffer has one of a pull-up function and a pull-down function, and the third replica buffer has the other of the pull-up function and a pull-down function.
15. A semiconductor device comprising:
a first replica buffer coupled to a first calibration terminal;
a second replica buffer coupled to a second calibration terminal;
a third replica buffer coupled to the second calibration terminal;
a first reference voltage generating circuit generating a first reference voltage that is subject to be adjustable to produce an adjusted first reference voltage;
a second reference voltage generating circuit generating a second reference voltage that is subject to be adjustable to produce an adjusted second reference voltage, and the adjusted first reference voltage and the adjusted second reference voltages being different from each other;
a first comparing circuit comparing a voltage of the first calibration terminal with the first reference voltage to control impedance of the first and second replica buffers; and
a second comparing circuit comparing a voltage of the second calibration terminal with the second reference voltage to control an impedance of the third replica buffer.
16. A data processing system comprising a data processor and a semiconductor device, the semiconductor device including:
a first replica buffer coupled to a first calibration terminal;
a second replica buffer coupled to a second calibration terminal;
a third replica buffer coupled to the second calibration terminal;
a first reference voltage generating circuit generating a first reference voltage that is subject to be adjustable;
a second reference voltage generating circuit generating a second reference voltage that is fixed;
a first comparing circuit comparing a voltage of the first calibration terminal with the first reference voltage to control impedance of the first and second replica buffers; and
a second comparing circuit comparing a voltage of the second calibration terminal with the second reference voltage to control an impedance of the third replica buffer.
17. A method comprising:
generating a first reference voltage;
generating a second reference voltage which is different from the first reference voltage;
comparing the first reference voltage with a voltage of a first calibration terminal to output a first control signal;
comparing the second reference voltage with a voltage of a second calibration terminal to output a second control signal; and
adjusting impedance of first to third replica buffers in response to the first and second control signal.
18. The method as claimed in claim 17 , wherein the adjusting comprises adjusting the impedance of first and second replica buffers in response to the first control signal, and adjusting the impedance of the third replica buffer in response to the second control signal after the first and second replica buffers are adjusted.
19. The method as claimed in claim 18 , wherein the first replica buffer has one of a pull-up function and a pull-down function, and the third replica buffer has the other of the pull-up function and a pull-down function.