Injection locker frequency divider

1. An injection locked frequency divider, comprising:

a ring oscillator, which comprises a first delay cell and a second delay cell each comprising differential input terminals and differential output terminals, wherein the differential input terminals and the differential output terminals of the first delay cell are respectively coupled to the differential output terminals and the differential input terminals of the second delay cell;

a first injection unit, connected between the differential output terminals of the first delay cell, for receiving and injecting a first injection signal to the differential output terminals of the first delay cell; and

a second injection unit, connected between the differential output terminals of the second delay cell, for receiving and injecting a second injection signal to the differential output terminals of the second delay cell.

2. The divider according to claim 1 , wherein when each of the first injection signal and the second injection signal is a differential signal, the differential output terminals of the first or second delay cell output a first frequency-divided signal having a frequency substantially equal to one half of a frequency of the differential signal.

3. The divider according to claim 1 , wherein when the first and second injection signals are AC signals substantially equal to each other, the differential output terminals of the first and second delay cells output a second frequency-divided signal having a frequency substantially equal to one fourth of a frequency of each of the first and the second injection signals.

4. The divider according to claim 1 , wherein when the first and second injection signals are respectively equal to a first voltage level and an AC signal, the differential output terminals of the first and second delay cells output a second frequency-divided signal having a frequency substantially equal to one fourth of a frequency of the AC signal.

5. The divider according to claim 1 , wherein each of the first and second delay cells comprises:

a first inverter unit and a second inverter unit, having input terminals respectively coupled to the corresponding differential input terminals in the corresponding delay cells, and output terminals respectively coupled to the corresponding differential output terminals in the corresponding delay cells, for generating a first inverted signal and a second inverted signal according to signals of the differential input terminals and outputting the first inverted signal and the second inverted signal to the corresponding differential output terminals; and

a first cross latch unit, coupled to the first and second inverter units, for latching the first and second inverted signals.

6. The divider according to claim 5 , wherein each of the first inverter unit and the second inverter unit comprises:

a first transistor and a second transistor having first terminals respectively receiving a second voltage level and a third voltage level, second terminals coupled to the corresponding differential output terminals, and control terminals coupled to the corresponding differential input terminals.

7. The divider according to claim 5 , wherein the first cross latch unit comprises:

a third transistor and a fourth transistor having first terminals receiving the second voltage level, second terminals respectively coupled to the corresponding differential output terminals in the corresponding delay cells, and control terminals respectively coupled to the second terminals of the fourth and third transistors.

8. The divider according to claim 5 , wherein each of the first and second delay cells further comprises a second cross latch unit for latching the first and second inverted signals, and the second cross latch unit comprises:

a fifth transistor and a sixth transistor having first terminals receiving the third voltage level, second terminals respectively coupled to the corresponding differential output terminals in the corresponding delay cells, and control terminals respectively coupled to the second terminals of the fourth and third transistors.

9. The divider according to claim 1 , wherein the first injection unit comprises:

a first transistor having a first terminal and a second terminal respectively coupled to the differential output terminals of the first delay cell, and a control terminal receiving the first injection signal.

10. The divider according to claim 1 , wherein the second injection unit comprises:

a second transistor having a first terminal and a second terminal respectively coupled to the differential output terminals of the second delay cell, and a control terminal receiving the second injection signal.

11. The divider according to claim 1 , further comprising:

a switching unit, coupled to the first and second delay cells, for responding with a selection signal to change a natural frequency of the ring oscillator and thus to change an injection locked frequency range of the injection locked frequency divider.

12. The divider according to claim 1 , wherein the switching unit comprises:

a plurality of switches, each having a first terminal and a second terminal, for responding with a selection signal to electrically connect the first terminal to the second terminal, wherein the first terminal of each of the switches receives a third voltage level; and

a plurality of capacitors having first terminals respectively coupled to the second terminals of the switches, and second terminals coupled to the differential output terminals of the first and second delay cells,

wherein when the switches turn on, the capacitors change natural frequencies of the first and second delay cells and thus change an injection locked frequency range of the injection locked frequency divider.