Method of manufacturing a semiconductor device having an interconnect structure that increases in impurity concentration as width increases
View Patent ↗The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains.
1. A method of manufacturing semiconductor device including an interconnect, comprising:
forming on a semiconductor substrate an insulating layer in which a wide interconnect trench which is relatively wide, and a narrow interconnect trench which is relatively narrow are formed;
forming by a sputtering method a relatively thick alloy layer including a metal containing an impurity in said bottom of wide interconnect trench, and a relatively thin alloy layer including a metal containing an impurity in said bottom of narrow interconnect trench;
forming a metal layer including the same metal as that of said metal layer on both of said alloy layers in said wide interconnect trench and in said narrow interconnect trench;
diffusing said impurity from said alloy layer into said metal layer, so as to form a metal layer having a relatively high impurity concentration in said wide interconnect trench, and a metal layer having a relatively low impurity concentration in said narrow interconnect trench; and
removing said alloy layer and said metal layer formed in an external region of said respective interconnect trenches, so as to form a relatively wide interconnect in said wide interconnect trench and a relatively narrow interconnect in said narrow interconnect trench, so as to constitute a first interconnect.
2. The method according to claim 1 , wherein said step of diffusing said impurity from said alloy layer into said metal layer includes performing a heat treatment for granulating said metals so as to diffuse said impurity.
3. The method according to claim 1 , wherein said step of forming a metal layer including the same metal as that of said metal layer includes performing an electrolytic plating method so as to form a metal layer on said alloy layer including the same metal as that of said metal layer.
4. The method according to claim 1 , further comprising:
forming on said first interconnect an interlayer dielectric layer in which an opening for a via plug is formed;
filling said opening for a via plug with a first conductive layer so as to form a via plug;
forming an interlayer dielectric layer in which a second interconnect trench connected to said via plug is provided; and
filling said second interconnect trench with a second conductive layer so as to form a second interconnect.
5. The method according to claim 4 , wherein said first conductive layer is constituted of one selected out of a group consisting of copper containing an impurity other than copper, copper, tungsten, and aluminum.
6. The method according to claim 1 , further comprising:
forming on said first interconnect an interlayer dielectric layer in which an opening for a via plug is formed and a second interconnect trench connected to said opening for a via plug is formed; and
filling said opening for a via plug and said second interconnect trench with a conductive layer, so as to form a via plug and a second interconnect.
7. The method according to claim 1 , wherein said metal is copper.
8. The method according to claim 1 , further comprising:
forming a third interconnect constituted of said metal not containing an impurity, on said first interconnect.