Output circuit of semiconductor device
View Patent ↗An output circuit of a semiconductor includes unit buffers, each unit buffer having transistors and resistors connected between a power source terminal VDDQ and an output terminal DQ, and transistors and resistors connected between a power source terminal VSSQ and an output terminal DQ. On-resistance values of transistors included in the unit buffers are mutually substantially the same, and resistance values of resistors included in the unit buffers are mutually different. A deviation of impedances attributable to a power source resistance can be offset based on a difference between resistance values of the resistors.
1. An output circuit of a semiconductor device comprising:
a first output buffer including one unit buffer having a series circuit of a transistor and a resistor;
a second output buffer having m unit buffers connected in parallel, each unit buffer having a series circuit of a transistor and a resistor; and
a third output buffer having n unit buffers connected in parallel, each unit buffer having a series circuit of a transistor and a resistor, wherein
ON resistance values of the transistors included in the first to the third output buffers are mutually substantially the same,
resistance values of the resistors included in the second output buffer are mutually substantially the same,
resistance values of the resistors included in the third output buffer are mutually substantially the same, and
resistance values of at least the two resistors included in the first to the third output buffers are different from each other.
2. The output circuit of a semiconductor device as claimed in claim 1 , wherein the resistance values of the resistor included in the first output buffer are different from the resistance values of the resistors included in the third output buffer.
3. The output circuit of a semiconductor device as claimed in claim 2 , wherein the resistance values of the resistors included in the third output buffer are lower than at least one of the resistance values of the resistors included in the first and the second output buffers.
4. The output circuit of a semiconductor device as claimed in claim 1 , wherein the resistance values of the resistors included in the second output buffer are different from the resistance values of the resistors included in the third output buffer.
5. The output circuit of a semiconductor device as claimed in claim 1 , wherein the resistance values of the resistor included in the first output buffer are substantially the same as the resistance values of the resistors included in the second output buffer.
6. The output circuit of a semiconductor device as claimed in claim 1 , wherein m is equal to 2 and n is equal to 3,
when one unit buffer is used, the first output buffer is selected,
when two unit buffers are used, the second output buffer is selected,
when three unit buffers are used, the first and the second output buffers are selected simultaneously,
when four unit buffers are used, the first and the third output buffers are selected simultaneously,
when five unit buffers are used, the second and the third output buffers are selected simultaneously, and
when six unit buffers are used, the first to the third output buffers are selected simultaneously.
7. The output circuit of a semiconductor device as claimed in claim 1 , further comprising a fourth output buffer including one unit buffer having a series circuit of a transistor and a resistor, wherein
ON resistance values of the transistors included in the first to the fourth output buffers are mutually substantially the same, and
resistance values of the resistor included in the fourth output buffer are different from resistance values of the resistors included in the first to the third output buffers.
8. The output circuit of a semiconductor device as claimed in claim 7 , wherein resistance values of the resistors included in the fourth output buffer are lower than resistance values of the resistors included in the first to the third output buffers.
9. The output circuit of a semiconductor device as claimed in claim 7 , wherein when seven unit buffers are selected, the first to the fourth output buffers are selected simultaneously.
10. The output circuit of claim 1 , further comprising:
a first pre-stage circuit connected to the first output buffer;
a second pre-stage circuit connected to the second output buffer; and
a third pre-stage circuit connected to the third output buffer.