Method of manufacturing a semiconductor device that includes forming a via hole through a reaction layer formed between a conductive barrier and a wiring
View Patent ↗Provided are: a method of manufacturing semiconductor device which has multilayer interconnection in a damascene structure and a conductive barrier film such as CoWP film, and which has more excellent electric characteristics than a conventional one. To this end, when a via hole reaching a lower wiring is formed, a reaction layer formed between a conductive barrier film and the lower wiring and remaining on the surface of the lower wiring is removed. Thus, at an interface where a lower surface of the via and the lower wiring are joined, the reaction layer, formed between the conductive barrier film and the lower wiring, does not exist, so that the via resistance can be sufficiently reduced.
1. A method of manufacturing a semiconductor device having a multilayer interconnection formed in a damascene structure, comprising:
forming a lower wiring in a first interlayer insulation film;
forming a conductive barrier film on the lower wiring;
forming a second interlayer insulation film covering the first interlayer insulation film and the conductive barrier film;
forming a via hole, which reaches the lower wiring, in the second interlayer insulation film and the conductive barrier film,
wherein the forming the via hole includes removing a reaction layer formed between the conductive barrier film and the lower wiring;
forming a barrier metal film on an entire surface, during a period between the formation of the via hole in the second interlayer insulation film and the formation of the via hole in the conductive barrier film, so that the barrier metal film should cover the via hole in the second interlayer insulation film; and
removing a barrier metal film from a bottom of the via hole during the period.
2. The method of manufacturing the semiconductor device according to claim 1 , wherein the lower surface of the via hole is lower than the upper surface of the lower wiring.
3. The method of manufacturing the semiconductor device according to claim 1 , wherein the lower wiring contains any of copper, aluminum, silver, and an alloy composed of these metals.
4. The method of manufacturing the semiconductor device according to claim 1 , wherein the conductive barrier film comprises material including Cobalt.
5. The method of manufacturing the semiconductor device according to claim 1 , wherein the conductive barrier film comprises any of CoWP and CoWB.
6. The method of manufacturing the semiconductor device according to claim 1 , wherein at least one of the first interlayer insulation film and the second interlayer insulation film is comprises a low dielectric constant film with a dielectric constant of 2.5 or less.
7. The method of manufacturing the semiconductor device according to claim 1 , wherein at least one of the first interlayer insulation film and the second interlayer insulation film comprises a low dielectric constant film having a porous structure.
8. The method of manufacturing the semiconductor device according to claim 1 , wherein the barrier metal film comprises any one of a Ta film, a TaN film, a WN film, a Ti film, a TiN film, a Ru film, a RuN film, and a laminated film formed of these films.
9. A method of manufacturing a semiconductor device, comprising:
forming a first wiring layer;
covering the first wiring layer with a conductive barrier film;
forming an interlayer insulating film on the conductive barrier film, a reaction layer being formed between the first wiring layer and the conductive barrier film;
removing respective portions of interlayer insulating film, the reaction layer and the conductive barrier film to form a via hole that exposes a portion of the first wiring layer;
forming a barrier metal film on an entire surface, during a period between the formation of the via hole in the interlayer insulation film and the formation of the via hole in the conductive barrier film, so that the barrier metal film should cover the via hole in the interlayer insulation film; and
removing a barrier metal film from a bottom of the via hole during the period.
10. The method of manufacturing the semiconductor device according to claim 9 , wherein the lower surface of the via hole is lower than the upper surface of the first wiring layer.
11. The method of manufacturing the semiconductor device according to claim 9 , wherein the conductive barrier film comprises material including Cobalt.
12. The method of manufacturing the semiconductor device according to claim 9 , wherein the conductive barrier film comprises any of CoWP and CoWB.
13. The method of manufacturing the semiconductor device according to claim 9 , wherein the first wiring layer contains any of copper, aluminum, silver, and an alloy composed of these metals.
14. The method of manufacturing the semiconductor device according to claim 9 , wherein the interlayer insulation film comprises a low dielectric constant film with a dielectric constant of 2.5 or less.
15. The method of manufacturing the semiconductor device according to claim 9 , wherein the interlayer insulation film comprises a low dielectric constant film having a porous structure.
16. The method of manufacturing the semiconductor device according to claim 9 , wherein the barrier metal film comprises any one of a Ta film, a TaN film, a WN film, a Ti film, a TiN film, a Ru film, a RuN film, and a laminated film formed of these films.