Bistable circuit with auto-time-adjusted switching, and flip-flop using such a bistable circuit
Bistable circuit switching at the edges of a clock signal, including means for pre-charging an intermediate node of the circuit, delay means including a chain of inverters defining a time window around an edge of said clock signal, means for discharging the intermediate node controlled by at least one input data item making it possible to discharge the intermediate node for the duration of said time window, characterized in that the delay means include means for temporally adjusting the duration of the time window to the time for discharging the intermediate node through said discharge means.
1. Bistable circuit switching at the edges of a clock signal, including means for pre-charging an intermediate node of the circuit, delay means including a chain of inverters defining a time window around an edge of said clock signal, means for discharging the intermediate node controlled by at least one input data item and including a path of nMos transistors connected in series between the pre-charge means and a ground of the circuit, making it possible to discharge the intermediate node for the duration of said time window, wherein the delay means include means for temporally adjusting the duration of the time window to the time for discharging the intermediate node through said discharge means, wherein said time adjustment means are integrated at the level of an inverter of the inverter chain, in the form of a path of nMos transistors replicating the transistor path of the discharge means, connected in series with a pMos transistor of said inverter.
2. Circuit according to claim 1 , wherein the means for discharging the intermediate node also include a logic combination stage between at least two input data items of the circuit.
3. Circuit according to claim 2 , wherein the logic combination stage includes a network of transistors arranged in the transistor path of the discharge means so as to perform a predetermined logic function between the input data items, wherein said transistors constituting the logic combination stage are each controlled respectively by one of the input data items.
4. Circuit according to claim 1 , wherein a transistor battery of a modified inverter of the delay chain includes the same number of stages as the transistor path of the means for discharging the intermediate node.
5. Circuit according to claim 1 , wherein the transistor path of a modified inverter of the delay chain includes fewer stages than the transistor path of the means for discharging the intermediate node.
6. A latch, comprising:
a first node;
a first circuit having a first configuration of components, the first circuit operable to drive a data signal onto the first node a first time after being enabled; and
a second circuit having at least the first configuration of components, the second circuit operable to disable the first circuit a second time after the first circuit is enabled, the second time being equal to a sum of a pre-established delay time and substantially the first time.
7. The latch of claim 6 wherein the second circuit is operable to:
generate a disable signal substantially the first time after receiving a clock signal; and
disable the first circuit the pre-established delay time after generating the disable signal.
8. The latch of claim 6 wherein:
the first node comprises an output node; and
the data signal comprises an output data signal.
9. The latch of claim 6 , further comprising:
an output node; and
a third circuit operable to drive an output data signal onto the output node after receiving the data signal.
10. A latch, comprising:
a first node;
a first circuit operable to drive a data signal onto the first node a first time after being enabled;
a second circuit operable to disable the first circuit a second time after the first circuit is enabled, the second time being equal to a sum of a pre-established delay time and substantially the first time; and
wherein the first circuit is operable to generate the data signal as a logical combination of a first input data signal and a second input data signal.
11. The latch of claim 6 wherein the first circuit is operable to generate the data signal in response to an input data signal.
12. A circuit, comprising:
a first node operable to hold a first charge level;
a first path coupled to the first node, operable to receive a first control signal, and operable to transition the first node from the first charge level to a second charge level a first delay time after the control signal transitions to a first signal level, the first path having a first delay circuit for causing the first delay time;
a second node operable to hold a third charge level and coupled directly to an element in the first path;
a second path coupled to the second node, operable to receive a second control signal, and operable to transition the second node from the third charge level to a fourth charge level approximately the first delay time after the second control signal transitions to a second signal level, the second path having a second delay circuit substantially similar to the first delay circuit for causing at least the first delay time; and
a signal generator coupled to the second node and operable to transition the first control signal to the first signal level a pre-established time after the second node transitions to the fourth charge level.
13. The circuit of claim 12 wherein:
the first path comprises a first set of transistors serially coupled between the first node and a third node; and
the second path comprises a second set of transistors serially coupled between the second node and the third node.
14. An integrated circuit, comprising:
a first node;
a first circuit having a first configuration of components, the first circuit operable to drive a data signal onto the first node a first time after being enabled; and
a second circuit having at least the first configuration of components, the second circuit operable to disable the first circuit a second time after the first circuit is enabled, the second time being equal to a sum of a pre-established delay time and substantially the first time.
15. A system, comprising:
a first integrated circuit, comprising,
a first node,
a first circuit having a first configuration of components, the first circuit operable to drive a data signal onto the first node a first time after being enabled, and
a second circuit having at least the first configuration of components, the second circuit operable to disable the first circuit a second time after the first circuit is enabled, the second time being equal to a sum of a pre-established delay time and substantially the first time; and
a second integrated circuit coupled to the first integrated circuit.
16. The system of claim 15 wherein:
the first integrated circuit is disposed on a first die; and
the second integrated circuit is disposed on a second die.
17. The system of claim 15 wherein the first and second integrated circuits are disposed on a same die.
18. The system of claim 15 wherein the second integrated circuit comprises a controller.
19. A method, comprising:
enabling generation of a first signal from a second signal;
generating the first signal from the second signal a first delay time after the enabling, the first delay time caused by a first delay circuit having a first configuration of components;
disabling generation of the first signal from the second signal a second delay time after the enabling, the second delay time being equal to a sum of a pre-established delay time and substantially the first delay time, the second delay time caused by a second delay circuit having at least the first configuration of components.
20. The method of claim 19 wherein:
the enabling comprises causing a latch to enter a transparent state; and
the disabling comprises latching the first signal.
21. The method of claim 19 wherein:
the enabling comprises enabling generation of the first signal from a second signal in response to a clock edge; and
the disabling comprises disabling generation of the second signal in response to the clock edge.
22. The method of claim 19 wherein enabling generation of the first signal comprises enabling generation of the first signal from a combination of the second signal and a third signal.
23. An integrated circuit, comprising:
a delay circuit having an input node operable to receive a clock signal, an output node, and a plurality of delay elements serially coupled between the input and output nodes, wherein at least one delay element comprises a configuration for causing a first delay; and
a buffer that is substantially the same as the at least one of the delay elements, the buffer causing a second delay that consists of at most the first delay and including a first input node operable to receive the clock signal, a second input node coupled to the output node of the delay circuit, and an output node.
24. The integrated circuit of claim 23 wherein the buffer comprises an inverter including a plurality of serially coupled transistors wherein at least one transistor comprises a P-type MOS transistor and at least one transistor comprises an N-type MOS transistor and wherein the at least one delay element that is substantially the same as the buffer comprises an inverter including a plurality of serially coupled transistors wherein at least one transistor comprises a P-type MOS transistor that is substantially the same as the P-type MOS transistor of the buffer and at least one transistor comprises an N-type MOS transistor that is substantially the same as the at least one N-type MOS transistor of the buffer.
25. The integrated circuit of claim 23 wherein the buffer comprises a third input node operable to receive a data signal.
26. The integrated circuit of claim 23 wherein the buffer comprises:
a P-type MOS transistor having a control node coupled to the input node of the delay circuit, a first drain/source node coupled to a first supply node and a second drain source node coupled to the output node of the buffer;
a first N-type MOS transistor having a control node coupled to output node of the delay circuit, a first drain/source node coupled to the output node of the buffer and a second drain/source node;
a second N-type MOS transistor having a control node coupled to a third input node of the buffer, a first drain/source node coupled to the second drain/source node of the first N-type MOS transistor and a second drain/source node; and
a third N-type MOS transistor having a control node coupled to the input node of the delay circuit, a first drain/source node coupled to the second drain/source node of the second N-type MOS transistor and a second drain/source node coupled to a second supply node.
27. An integrated circuit, comprising:
a delay circuit having an input node operable to receive a clock signal, an output node, and a plurality of delay elements serially coupled between the input and output nodes; and
a buffer that is substantially the same as at least one of the delay elements, the buffer including a first input node operable to receive the clock signal, a second input node coupled to the output node of the delay circuit, and an output node;
wherein the delay circuit comprises:
a P-type MOS transistor having a control node coupled to the input node of the delay circuit, a first drain/source node coupled to a first supply node and a second drain/source node;
a first N-type MOS transistor having a control node coupled to the input node of the delay circuit, a first drain/source node coupled to the second drain/source node of the P-type MOS transistor and a second drain/source node;
a second N-type MOS transistor having a control node coupled to a input node of the delay circuit, a first drain/source node coupled to the second drain/source node of the first N-type MOS transistor and a second drain/source node; and
a third N-type MOS transistor having a control node coupled to the input node of the delay circuit, a first drain/source node coupled to the second drain/source node of the second N-type MOS transistor and a second drain/source node coupled to a second supply node.
28. The integrated circuit of claim 23 wherein each delay element comprises an inverter.
29. An integrated circuit, comprising:
a delay circuit having an input node operable to receive a clock signal, an output node, and a plurality of delay elements serially coupled between the input and output nodes; and
a buffer that is substantially the same as at least one of the delay elements, the buffer including a first input node operable to receive the clock signal, a second input node coupled to the output node of the delay circuit, and an output node;
wherein the buffer further comprises:
a third input node operable to receive a first data signal;
a fourth input node operable to receive a second data signal; and
a second output node operable to generate the resultant data signal that comprises a logical combination of the first data signal and the second data signal.
30. A system, comprising:
an integrated circuit, including:
a delay circuit having an input node operable to receive a clock signal, an output node, and a plurality of delay elements serially coupled between the input and output nodes, wherein at least one delay element comprises a configuration for causing a first delay; and
a buffer that is substantially the same as the at least one of the delay elements, the buffer causing a second delay that consists of at most the first delay and including a first input node operable to receive the clock signal, a second input node coupled to the output node of the delay circuit, and an output node.