Soft error rate calculation method and program, integrated circuit design method and apparatus, and integrated circuit

1. A calculation method of a soft error rate of a storage circuit or an information holding circuit, comprising:

deriving a first mathematical expression indicating a dependence of a soft error rate on an information storage node diffusion layer area at the same information storage node voltage from a measurement result of a relationship between a soft error rate and the information storage node diffusion layer area of a storage circuit or an information holding circuit composed of a transistor with use of a plurality of information storage node voltages as a parameter;

deriving a second mathematical expression indicating a soft error rate as a function of the information storage node diffusion layer area and the information storage node voltage by substituting a relationship indicating a dependence of a soft error rate on the information storage node voltage at the same information storage node diffusion layer area into the first mathematical expression; and

calculating a soft error rate by substituting a desired information storage node diffusion layer area and a desired information storage node voltage into the second mathematical expression.

2. The calculation method of a soft error rate according to claim 1 , wherein

the first mathematical expression satisfies:

SER= f*Sc ^( g ) or SER= f *exp( g*Sc )

where SER is the soft error rate, Sc is the information storage node diffusion layer area, and f and g are fitting parameters.

3. The calculation method of a soft error rate according to claim 2 , wherein

the second mathematical expression satisfies:

SER=( a*Vn^b )* Sc ^( p *exp( q*Vn )) or

SER=( a*Vn^b )* Sc ^( p*Vn+q )

where SER is the soft error rate, Sc is the information storage node diffusion layer area, Vn is the information storage node voltage, and a, b, p and q are fitting parameters.

4. The calculation method of a soft error rate according to claim 2 , further comprising:

determining a value of a such that

SER∝ F ( Sc ), Sc=Scn+a*Scp

fits best with an actual measurement value, where Scn is the information storage node diffusion layer area composed of an n-type transistor, Scp is the information storage node diffusion layer area composed of a p-type transistor, F(Sc) is a function of the information storage node diffusion layer area Sc, and a is a constant in the storage circuit or the information holding circuit.

5. The calculation method of a soft error rate according to claim 1 , wherein

the second mathematical expression satisfies:

SER=( a*Vn^b )* Sc ^( p *exp( q*Vn )) or

SER=( a*Vn^b )* Sc ^( p*Vn+q )

where SER is the soft error rate, Sc is the information storage node diffusion layer area, Vn is the information storage node voltage, and a, b, p and q are fitting parameters.

6. The calculation method of a soft error rate according to claim 5 , further comprising:

determining a value of a such that

SER∝ F ( Sc ), Sc=Scn+a*Scp

fits best with an actual measurement value, where Scn is the information storage node diffusion layer area composed of the n-type transistor, Scp is the information storage node diffusion layer area composed of a p-type transistor, F(Sc) is a function of the information storage node diffusion layer area Sc, and a is a constant in the storage circuit or the information holding circuit.

7. The calculation method of a soft error rate according to claim 5 , wherein

Vn(1+Ca/Co)

is substituted into Vn of the second mathematical expression where Ca is a capacitance of a capacitor added above the storage node diffusion layer to avoid direct collection of carries from a substrate, Vn is the storage node voltage of the storage circuit or the information holding circuit, and Co is a storage node capacitance.

8. The calculation method of a soft error rate according to claim 1 , further comprising:

measuring a soft error rate with different sizes of a p-type transistor and an n-type transistor constituting the storage circuit or the information holding circuit.

9. The calculation method of a soft error rate according to claim 1 , further comprising:

calculating a converted information storage node diffusion layer area and/or a converted information storage node voltage, when the calculated soft error rate is equal to or larger than a prescribed value, by changing at least one of the information storage node diffusion layer area, the information storage node voltage and a manufacturing process; and

recalculating a soft error rate by substituting the converted information storage node diffusion layer area and/or the converted information storage node voltage into the second mathematical expression.

10. The calculation method of a soft error rate according to claim 9 , wherein

the converted information storage node diffusion layer area is a converted value when a drain area of the transistor is changed.

11. The calculation method of a soft error rate according to claim 9 , wherein

the converted information storage node diffusion layer area is a converted value corresponding to an amount of carries generated by radiation and collected into the information storage node diffusion layer.

12. The calculation method of a soft error rate according to claim 11 , wherein

the amount of carries generated by radiation and collected into the information storage node diffusion layer is a simulation value or a measurement value of a test device.

13. The calculation method of a soft error rate according to claim 9 , wherein

the converted information storage node voltage varies corresponding to a capacitance of the capacitor added above the diffusion layer of the transistor.

14. The calculation method of a soft error rate according to claim 1 , wherein

the storage circuit or the information holding circuit is composed of MISFET.

15. A design apparatus of a semiconductor integrated circuit including a storage circuit or an information holding circuit composed of a transistor, comprising:

a first mathematical expression deriving unit to derive a first mathematical expression indicating a dependence of a soft error rate on an information storage node diffusion layer area at the same information storage node voltage from a measurement result of a relationship between a soft error rate and the information storage node diffusion layer area of the storage circuit or the information holding circuit with use of a plurality of information storage node voltages as a parameter;

a second mathematical expression deriving unit to derive a second mathematical expression indicating a soft error rate as a function of the information storage node diffusion layer area and the information storage node voltage by substituting a relationship indicating a dependence of a soft error rate on the information storage node voltage at the same information storage node diffusion layer area into the first mathematical expression; and

a SER calculation unit to calculate a soft error rate by substituting a desired information storage node diffusion layer area and a desired information storage node voltage into the second mathematical expression.

16. The design apparatus of a semiconductor integrated circuit according to claim 15 , further comprising:

a SER evaluation unit to evaluate a soft error rate calculated by the SER calculation unit.

17. The design apparatus of a semiconductor integrated circuit according to claim 15 , wherein

when the calculated soft error rate is equal to or larger than a prescribed value, the SER evaluation unit causes input of a converted information storage node diffusion layer area and/or a converted information storage node voltage calculated by changing at least one of the information storage node diffusion layer area, the information storage node voltage and a manufacturing process; and

the SER calculation unit recalculates a soft error rate by substituting the converted information storage node diffusion layer area and/or the converted information storage node voltage into the second mathematical expression.

18. A static random memory (SRAM) device comprising;

a plurality of cells; and

a peripheral circuit;

wherein an area of one storage node diffusion layer of the cells is smaller than about 0.04 μm 2 , and

wherein a selected cell of the cells receives a power supply voltage higher than that of a non-selected cell of the cells and the power supply voltage is as the same as a power supply voltage for the peripheral circuit.

19. The SRAM device according to claim 18 , wherein the supply voltage of the non-selected cell is lower than that of the selected cell, and is higher than a minimum voltage to hold an information of the cells.