IP Library Granted Patent US 7,589,587
Granted Patent B2
US 7,589,587 · App. 11/896,899 · Granted Sep 15, 2009

Feedback amplifier circuit operable at low voltage by utilizing switched operational amplifier and chopper modulator

Assignee: Semiconductor Technology Academic Research Center
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Quick Facts
Patent No.
US 7,589,587
App. No.
11/896,899
Granted
Sep 15, 2009
Kind
B2
Abstract

In a feedback amplifier circuit, a first switching device executes an auto-zero operation by inputting a signal outputted from an amplifier to an input terminal of the amplifier during an auto-zero operation interval prior to an amplification interval. A first capacitor accumulates and holds an offset voltage at the output terminal of the amplifier during the auto-zero operation interval, and cancels an offset voltage at the input terminal of the amplifier by an accumulated and held offset voltage during an amplification interval subsequent to the auto-zero operation interval. A second switching device grounds the feedback point of the feedback circuit during the auto-zero operation interval. A second capacitor blocks a DC voltage, and accumulates and holds an offset voltage at an output terminal of the amplifier, and cancels an offset voltage at an input terminal of the amplifier by the accumulated and held offset voltage during an amplification interval.

Claims (17)

1. A feedback amplifier circuit comprising:

an amplifier for amplifying an input signal and outputting an amplified signal;

a first switching device for executing an auto-zero operation by inputting a signal outputted from the amplifier to an input terminal of the amplifier during an auto-zero operation interval prior to an amplification interval;

a first capacitor provided in a feedback circuit interposed between an output terminal of the amplifier and the input terminal of the amplifier, the first capacitor accumulating and holding an offset voltage at the output terminal of the amplifier during the auto-zero operation interval, and then canceling an offset voltage at the input terminal of the amplifier by an accumulated and held offset voltage during an amplification interval subsequent to the auto-zero operation interval;

a second switching device for grounding the feedback point of the feedback circuit during the auto-zero operation interval;

a second capacitor inserted between the input terminal of the amplifier and the feedback point of the feedback circuit so as to be connected in series with the first capacitor, the second capacitor blocking a DC voltage, and accumulating and holding an offset voltage at an output terminal of the amplifier during the auto-zero operation interval, and thereafter cancelling an offset voltage at an input terminal of the amplifier by the offset voltage accumulated and held together with the first capacitor during an amplification interval subsequent to the auto-zero operation interval.

2. The feedback amplifier circuit as claimed in claim 1 , further comprising an analog switch circuit connected at a feedback point of the feedback circuit, the analog switch circuit being turned on and off to constitute a switched capacitor during the amplification interval.

3. The feedback amplifier circuit as claimed in claim 1 , further comprising:

a first chopper modulator for chopper-modulating an input signal according to a predetermined control signal and outputting a chopper-modulated signal to the amplifier via the second capacitor;

a chopper demodulator provided at a final stage of the amplifier, the chopper demodulator chopper-demodulating an amplified chopper-modulated signal according to the control signal and outputting a demodulated output signal; and

a second chopper modulator inserted in the feedback circuit, the second chopper modulator chopper-modulating a demodulated signal outputted from the chopper demodulator according to the control signal and outputting a chopper-modulated signal to an input terminal of the amplifier via the second capacitor, thereby constituting a chopper amplifier circuit.

4. The feedback amplifier circuit as claimed in claim 1 , further comprising a low-pass filter for passing therethrough an amplified input signal by low-pass-filtering an output signal outputted from the amplifier so as to pass therethrough a frequency band of the input signal.

5. The feedback amplifier circuit as claimed in claim 1 ,

wherein the feedback amplifier circuit is constituted as a fully-differential amplifier circuit, and

wherein the feedback amplifier circuit further comprises a common mode feedback circuit for generating a feedback signal fed back to the input terminal of the amplifier so that a level of the output signal outputted from the amplifier becomes a predetermined reference value in a common mode, based on an output signal outputted from the amplifier.

6. The feedback amplifier circuit as claimed in claim 1 ,

wherein the feedback amplifier circuit is formed by a CMOS circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2007
From: YOSHIDA, TAKESHI; MASUI, YOSHIHIRO; IWATA, ATSUSHI; GOTOH, KUNIHIKO
To: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
Reel/Frame 020177/0446 →
Priority Claims (1)
JP 2006-242728 · Sep 7, 2006 · national
Continuity (1)
Related Publication 20080106330A1 · May 8, 2008