Nonvolatile memory device and methods of fabricating and driving the same
View Patent ↗Nonvolatile memory devices and methods of fabricating and driving the same are disclosed. Disclosed devices and method comprises: growing an oxide layer on a substrate and depositing a nitride layer on the oxide layer; patterning the nitride layer; forming injection gates on the lateral faces of the nitride layer; depositing a first polysilicon, a dielectric layer and a second polysilicon on the surface of the resulting structure, sequentially; patterning the second polysilicon, the dielectric layer and the second polysilicon to form gate electrodes; removing the nitride layer between the injection gates; forming source and drain extension regions around each of the gate electrodes by performing an ion implantation process; forming sidewall spacers on the lateral faces of the gate electrodes; and forming source and drain regions in the substrate by performing an ion implantation process with the sidewall spacers as an ion implantation mask.
1. A method for fabricating a nonvolatile memory device comprising:
growing an oxide layer on a substrate;
depositing an insulating layer on the oxide layer;
patterning the insulating layer;
forming injection gates on the lateral faces of the insulating layer;
depositing a first polysilicon, a dielectric layer and a second polysilicon;
patterning the second polysilicon, the dielectric layer and the second polysilicon to form gate structures;
removing the insulating layer between the injection gates;
forming source and drain extension regions around each of the gate structures by ion implantation;
forming sidewall spacers on the lateral faces of the gate structures; and
forming source and drain regions in the substrate by ion implantation, using the sidewall spacers as an ion implantation mask.
2. The method according to claim 1 , further comprising removing the oxide layer and forming a tunnel oxide layer before forming the injection gates.
3. The method according to claim 2 , wherein the tunnel oxide layer has a thickness between 60 Å and 120 Å.
4. The method according to claim 1 , wherein the injection gates comprise a material whose band gap is greater than that of silicon and less than that of SiO 2 .
5. The method according to claim 3 , wherein the insulating layer includes a nitride layer.
6. The method according to claim 1 , wherein the injection gates comprise an oxide material selected from the group consisting of Al 2 O 3 , Y 2 O 3 , ZrO 2 , BaZrO 2 , BaTiO 3 , Ta 2 O 5 , CaO, SrO, BaO, La 2 O 3 , Ce 2 O 3 , Pr 2 O 3 , Nd 2 O 3 , Pm 2 O 3 , Sm 2 O 3 , Eu 2 O 3 , Gd 2 O 3 , Tb 2 O 3 , Dy 2 O 3 , Ho 2 O 3 , Er 2 O 3 , Tm 2 O 3 , Yb 2 O 3 and Lu 2 O 3 .
7. The method according to claim 1 , wherein the injection gates comprise a material selected from the group consisting of SiC, AlP, AlAs, AlSb, GaP, GaAs, InP, ZnS, ZnSe, ZnTe, CdS, CdSe and CdTe.
8. The method according to claim 1 , wherein forming the injection gates comprises depositing a material for the injection gates at a thickness between 100 Å and 1000 Å, then performing a blanket etch.
9. The method according to claim 1 , wherein hot electron injection arises in the tunnel oxide layer under the injection gates.
10. The method according to claim 1 , wherein the insulating layer includes a nitride layer.
11. The method according to claim 1 , wherein the insulating layer has a thickness between 200 Å and 2500 Å.
12. The method according to claim 1 , wherein the dielectric layer comprises an ONO (Oxide-Nitride-Oxide) layer.
13. The method according to claim 1 , wherein the injection gates are in contact with the gate structures.
14. The method according to claim 1 , wherein the injection gates are aligned with lateral faces of the gate structures.