Semiconductor device and method of manufacturing the same

1. A method of manufacturing a semiconductor device having columnar gate electrodes, comprising:

forming plural holes in a row on a surface of a semiconductor substrate;

filling a first conductor into the plural holes to form plural columnar gate electrodes;

exposing a part in at least side faces of the gate electrodes to expose the plural columnar gate electrodes on a surface of the semiconductor substrate;

forming a gate sidewall film made of an insulator having a thickness larger than a half of a distance between the neighboring two columnar gate electrodes; and

planarizing upper ends of the plural columnar gate electrodes and forming a second gate electrode with a second conductor to junction upper ends of the plural columnar gate electrodes in a row.

2. The method according to claim 1 ,

wherein the forming of the plural holes includes:

forming a cover film on an SOI substrate formed by laminating the semiconductor substrate, an oxide film and an SOI region; and

forming the plural holes in a row by penetrating the SOI region and the cover film,

the forming of the plural columnar gate electrodes in a row includes:

forming a gate insulating film on an inside wall surface including bottom surfaces of the plural holes formed in a row; and

forming a conductor to form the plural columnar gate electrodes;

the exposing of the plural columnar gate electrodes removes the cover film to expose the plural columnar gate electrodes,

the forming of the gate sidewall film includes:

patterning a device separation film;

removing the gate insulating film and the columnar gate electrodes other than a device region to leave the gate insulating film and the columnar gate electrodes only in the device region; and

covering a gate sidewall film having a thickness larger than a half of an interval between the neighboring two columnar gate electrodes on the entire principal plane of the SOI substrate;

the forming of the second gate electrode includes:

etching back the gate sidewall film to leave the gate sidewall film only in a surrounding area of the columnar gate electrodes;

implanting an impurity ion into the SOI region in the device region at both sides of the sandwiched row of the plural columnar gate electrodes;

forming a metal film on an upper surface of the source and drain regions by using a salicide technique with respect to the device region;

forming an interlayer film made of a laminated film including a silicon nitride film and a silicon oxide film to cover the entire columnar gate electrodes and gate sidewall film;

planarizing an upper surface of the interlayer film until the columnar gate electrodes expose to form upper surfaces of the interlayer film, the gate sidewall film and the columnar gate electrodes as a planarized surface; and

junctioning the columnar gate electrodes on the planarized surface to electrically connect the columnar gate electrodes and to form a second gate electrode.

3. The method according to claim 1 ,

wherein the upper surfaces of the columnar gate electrodes are planarized, a nickel film is formed at a thickness larger than the thickness of the columnar gate electrodes on the planarized surface to perform heat treatment at a predetermined temperature, the nickel film is reacted with the columnar gate electrodes made of polysilicon to convert the entire columnar gate electrodes into NiSi, and non-reactive nickel film is removed.

4. The method according to claim 1 ,

wherein the forming of the plural holes includes:

forming a device separation region to surround a device region including a region to form a gate electrode in the semiconductor substrate;

forming a cover film on an upper surface of the device region and the device separation region; and

penetrating the device region and the cover film to form the plural holes in a row,

the forming of the plural columnar gate electrodes includes:

implanting an impurity ion of conduction type different from that of source and drain regions on bottom surfaces of the plural holes at high-density to form a punch through stopper region;

forming a gate insulating film on an inside wall surface including the bottom surfaces of the plural holes; and

filling a conductor on the gate insulating film in the plural holes to form the plural columnar gate electrodes,

the exposing of the plural columnar gate electrodes removes the cover film to expose the plural columnar gate electrodes;

the forming of the gate sidewall film forms a gate sidewall film in a surrounding area of the columnar gate electrodes and the gate insulating film;

the forming of the second gate electrode includes:

using the punch through stopper region as a stopper, implanting an impurity ion at both ends of a sandwiched row of the plural columnar gate electrodes of the device region surrounded by the device separation region to form source and drain regions;

forming a metal film on an upper surface of the source and drain regions by using a salicide technique with respect to the device region;

forming an interlayer film made of a laminated film including a silicon nitride film and a silicon oxide film to cover the entire columnar gate electrodes and gate sidewall film;

planarizing an upper surface of the interlayer film until the columnar gate electrodes expose to form upper surfaces of the columnar gate electrodes as a planarized surface; and

junctioning the columnar gate electrodes on the planarized surface to electrically connect the columnar gate electrodes and to form a second gate electrode.

5. The method according to claim 1 ,

wherein the forming of the plural holes includes:

forming a device separation region to surround a device region including a region to form a gate electrode in the semiconductor substrate;

forming a cover film on an upper surface of the device region and the device separation region; and

penetrating the device region and the cover film to form the plural holes in a row,

the forming of the plural columnar gate electrodes includes:

implanting an impurity ion of conduction type different from that of source and drain regions on bottom surfaces of the plural holes at high-density to form a punch through stopper region; and

oxidizing an upper surface of the columnar gate electrodes made of polysilicon to form a gate cap film on the upper surfaces of the columnar gate electrodes;

forming a gate insulating film on an inside wall surface including bottom surfaces of the plural holes; and

filling polysilicon on the gate insulating film into the plural holes to form the plural columnar gate electrodes,

the exposing of the plural columnar gate electrodes removes the cover film to expose the plural columnar gate electrodes;

the forming of the gate insulating film forms a gate sidewall film in a surrounding area of the columnar gate electrodes and the gate insulating film;

the forming of the second gate electrode includes:

etching source and drain regions at both sides of the sandwiched row of the plural columnar gate electrodes having the gate sidewall film to form a recess region having the same depth as that of the punch through stopper region;

forming a epitaxial film on an upper surface of the recess region to form the source and drain regions including the epitaxial film, and forming a channel region distorted due to a stress of the epitaxial film between the source and drain regions;

removing the gate cap film from the upper surface of the columnar gate electrodes;

forming a metal layer on the upper surface of the columnar gate electrodes and the upper surface of the source and drain regions;

forming an interlayer film made of a laminated film including a silicon nitride film and a silicon oxide film to cover the entire columnar gate electrodes and gate sidewall film;

removing the upper surface of the interlayer film until the metal layer on the upper surface of the columnar gate electrodes expose; and

junctioning the upper surfaces of the interlayer film, the gate sidewall film and the columnar gate electrodes to electrically form a second gate electrode.

6. The method according to claim 1 ,

wherein the forming of the plural holes penetrates the SOI region in the SOI substrate formed by laminating the semiconductor substrate, the oxide film and the SOI region to form the plural holes in a row, and fills the oxide film into the plural holes to form plural columnar dummy gate electrodes;

the exposing of the plural columnar gate electrodes removes the SOI region other than a device region and etches the SOI region on the device region to expose a part of the columnar dummy gate electrodes;

the forming of the gate sidewall film includes:

forming the gate sidewall film to surround the partially exposed plural columnar dummy gate electrodes;

forming the source and drain regions by implanting an impurity ion into the SOI substrate; and

forming an etching stop film by oxidizing the surfaces of the source and drain regions;

the forming of the plural columnar gate electrodes includes:

covering the entire plural columnar dummy gate electrodes and gate sidewall film with polysilicon to form a dummy interlayer film;

planarizing the upper surface of the dummy interlayer film to expose the upper surfaces of the columnar dummy gate electrodes;

selectively etching the columnar dummy gate electrodes to open a gate forming section;

covering a gate oxide film on a bottom surface and a sidewall of the opened gate forming section;

filling a metal film on the gate oxide film in the gate forming section to form the columnar gate electrodes; and

oxidizing the upper surfaces of the columnar gate electrodes to form a gate cap film;

removing the dummy interlayer film, removing the etch stop film on the surfaces of the source and drain regions, and forming a metal film on the surfaces of the source and drain regions by using salicide technique;

forming an interlayer film made of a laminated film including a silicon nitride film and a silicon oxide film to cover the entire columnar gate electrode and gate sidewall film;

planarizing an upper surface of the interlayer film until the columnar gate electrodes expose to form upper surfaces of the interlayer film, the gate sidewall film and the columnar gate electrodes as a planarized surface; and

junctioning the columnar gate electrodes on the planarized surface to electrically connect the columnar gate electrodes to form a second gate electrode.

7. The method according to claim 1 ,

wherein the semiconductor substrate is an SOI substrate.

8. The method according to claim 1 ,

wherein the semiconductor substrate is a bulk substrate.

9. The method according to claim 1 ,

wherein each of the plural columnar gate electrodes is a round pillar.

10. The method according to claim 1 ,

wherein each of the plural columnar gate electrodes is an ellipse pillar.

11. The method according to claim 1 ,

wherein each of the plural columnar gate electrodes is a square pillar.