Semiconductor memory having ferroelectric capacitor
According to an aspect of the present invention, there is provided a semiconductor memory including a lower electrode, a first insulating region formed in the same layer as the lower electrode, a ferroelectric film formed on the lower electrode and on the first insulating region, an upper electrode formed on the ferroelectric film, a second insulating region formed in the same layer as the upper electrode and a transistor. The first insulating region partitions the lower electrode. The second insulating region partitions the upper electrode. The transistor includes a first impurity region connected to the lower electrode and a second impurity region connected to the upper electrode. At least one of the first insulating region and the second insulating region is formed by insulating the lower electrode or the upper electrode.
1. A semiconductor memory comprising:
a lower electrode;
a first insulating region that is formed in the same layer as the lower electrode and that partitions the lower electrode;
a ferroelectric film that is formed on the lower electrode and on the first insulating region;
an upper electrode formed on the ferroelectric film;
a second insulating region that is formed in the same layer as the upper electrode and that partitions the upper electrode; and
a transistor comprising:
a first impurity region connected to the lower electrode,
a second impurity region connected to the upper electrode, and
a channel region disposed between the first impurity region and the second impurity region;
wherein at least one of the first insulating region and the second insulating region is formed by insulating the lower electrode or the upper electrode,
wherein the lower electrode includes at least one material selected from a group consisting of Pt, Ir, IrO 2 , SrRuO 3 , Ru, RuO 2 , and La 1-x Sr x VO 3 (X<0.2), and
wherein the first insulating region comprises the material of the lower electrode and an insulating species.
2. The semiconductor memory according to claim 1 , wherein the second insulating region comprises a constituting element of the upper electrode and an insulating species.
3. The semiconductor memory according to claim 1 further comprising:
a first conducting region that is connected to the second impurity region and formed in the first insulating region; and
a second conducting region that is formed in the ferroelectric film and that electrically connects the first conducting region and the upper electrode.
4. The semiconductor memory according to claim 1 , wherein the second conducting region comprises a constituting element of the ferroelectric film and a constituting element of the upper electrode.
5. The semiconductor memory according to claim 1 , wherein the upper electrode comprises a pair of the upper electrodes;
wherein the pair of the upper electrodes respectively forms ferroelectric capacitors with the lower electrode.
6. The semiconductor memory according to claim 1 , wherein a capacitor formed by the lower electrode, the ferroelectric film, and the upper electrode comprises a plurality of ferroelectric capacitors adjacent to each other, and
wherein one of the ferroelectric capacitors shares at least one of the lower electrode and the upper electrode with the adjacent ferroelectric capacitor.
7. The semiconductor memory according to claim 1 further comprising:
a first oxygen barrier film that is disposed between the first impurity region and the lower electrode; and
a second oxygen barrier film that is disposed between the second impurity region and the first conducting region.
8. The semiconductor memory according to claim 1 further comprising:
an additional ferroelectric film that is formed on the upper electrode; and
an additional upper electrode that is formed on the additional ferroelectric film.
9. A semiconductor memory according to claim 1 , comprising:
a lower electrode;
a first insulating region that is formed in the same layer as the lower electrode and that partitions the lower electrode;
a ferroelectric film that is formed on the lower electrode and on the first insulating region;
an upper electrode formed on the ferroelectric film;
a second insulating region that is formed in the same layer as the upper electrode and that partitions the upper electrode; and
a transistor comprising:
a first impurity region connected to the lower electrode,
a second impurity region connected to the upper electrode, and
a channel region disposed between the first impurity region and the second impurity region;
wherein at least one of the first insulating region and the second insulating region is formed by insulating the lower electrode or the upper electrode,
wherein the upper electrode includes at least one material selected from a group consisting of Pt, Ir, IrO 2 , SrRuO 3 , Ru, RuO 2 , and La 1-x Sr x VO 3 (X<0.2), and
wherein the second insulating region comprises the material of the upper electrode and an insulating species.
10. A semiconductor memory comprising:
a lower electrode layer having a first conductive region and a first insulating region partitioning the lower electrode layer;
a ferroelectric film formed on the lower electrode layer;
an upper electrode layer formed on the ferroelectric film, the upper electrode layer having a conductive region and a second insulating region partitioning the upper electrode layer;
an insulating member formed beneath at least one of the first insulating region and the second insulating region; and
a transistor comprising:
a first impurity region connected to the first conductive region,
a second impurity region connected to the second conductive region, and
a channel region disposed between the first impurity region and the second impurity region,
wherein the lower electrode includes at least one material selected from a group consisting of Pt, Ir, IrO 2 , SrRuO 3 , Ru, RuO 2 , and La 1-x Sr x VO 3 (X<0.2), and
wherein the first insulating region comprises the material of the lower electrode and an insulating species.