IP Library Granted Patent US 7,933,465
Granted Patent B2
US 7,933,465 · App. 11/898,458 · Granted Apr 26, 2011

Processing data supply method and image processing apparatus

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Quick Facts
Patent No.
US 7,933,465
App. No.
11/898,458
Granted
Apr 26, 2011
Kind
B2
Abstract

When performing arithmetic processing on unprocessed image data with use of a target pixel and reference pixels in its proximity, buffers of a number corresponding to the number of lines required for the arithmetic processing, which are a first buffer and a second buffer, are used as intermediate storage units. Each buffer has a capacity that is smaller than a size of a line of the unprocessed image data and equal to or larger than a size required for the arithmetic processing in a main scanning direction. In each arithmetic processing, a pixel from each line in the unprocessed image data is input one by one to a storage region at the right end of a corresponding buffer, and a pixel is read and output from each position of each buffer that is determined according to a positional relationship between a target pixel and its reference pixel. Each time arithmetic processing is performed in each line, data is shifted one pixel from the right end to the left end in the first buffer and the second buffer.

Claims (37)

1. A processing data supply method when performing an arithmetic processing on unprocessed image data composed of a plurality of lines, each line containing a plurality of pieces of unit data of a prescribed size arranged sequentially in a main scanning direction, with a use of target unit data and reference unit data located in close proximity to the target unit data, as predetermined by the arithmetic processing, the method comprising:

placing intermediate storage units of a number corresponding to a number of lines required for the arithmetic processing, each intermediate storage unit including a plurality of storage regions of the prescribed size arranged sequentially from one end to another end and having a capacity smaller than a size of each line and equal to or larger than a size required for the arithmetic processing in the main scanning direction;

performing, in each arithmetic processing, an input process of inputting unit data one piece by one piece from each line of the unprocessed image data to a storage region at the one end as an input end of an intermediate storage unit corresponding to the line, and an output process of reading unit data stored in a storage region at each position determined according to a positional relationship between target unit data and reference unit data of the target unit data from each intermediate storage unit and supplying the unit data for the arithmetic processing; and

performing data shifting of each intermediate storage unit by one storage region from the one end to the other end each time the arithmetic processing is performed in each line.

2. The processing data supply method according to claim 1 , wherein the arithmetic processing uses processed data of unit data located before target unit data in a scanning order and in close proximity to the target unit data as reference unit data,

wherein the input process includes reading one piece of target unit data from a first memory to store the unprocessed image data and inputting the target unit data to a storage region at an input end of a prescribed intermediate storage unit, and reading processed data in a line containing unit data required for the arithmetic processing and being different from a line containing the target unit data one piece by one piece from a second memory to store the processed data and inputting the processed data to a storage region at an input end of an intermediate storage unit corresponding to the line and being different from the prescribed intermediate storage unit, and

wherein the method further comprises, upon each completion of the arithmetic processing, inputting processed data as a result of the arithmetic processing to a storage region adjacent to the storage region at the input end of the prescribed intermediate storage unit after the data shifting of the intermediate storage unit is performed.

3. The processing data supply method according to claim 1 , wherein the intermediate storage unit comprises a buffer.

4. The processing data supply method according to claim 2 , wherein the intermediate storage unit comprises a buffer.

5. The processing data supply method according to claim 1 , wherein the intermediate storage unit comprises a shift register.

6. The processing data supply method according to claim 2 , wherein the intermediate storage unit comprises a shift register.

7. The processing data supply method according to claim 1 , wherein the unit data comprises data of one pixel.

8. The processing data supply method according to claim 2 , wherein the unit data comprises data of one pixel.

9. The processing data supply method according to claim 1 , wherein a capacity of each intermediate storage unit is a sum of a distance between two most distant pieces of unit data located in the same line and required for a one-time arithmetic processing, and a double of the prescribed size of unit data.

10. The processing data supply method according to claim 2 , wherein a capacity of each intermediate storage unit is a sum of a distance between two most distant pieces of unit data located in the same line and required for a one-time arithmetic processing, and a double of the prescribed size of unit data.

11. An image processing apparatus to perform arithmetic processing on unprocessed image data composed of a plurality of lines, each line containing a plurality of pieces of unit data of a prescribed size arranged sequentially in a main scanning direction, with use of target unit data and reference unit data located in a close proximity to the target unit data, as predetermined by the arithmetic processing, the apparatus comprising:

intermediate storage units of a number corresponding to a number of lines required for arithmetic processing, each intermediate storage unit including a plurality of storage regions of the prescribed size arranged sequentially from one end to another end, having a capacity smaller than a size of each line and equal to or larger than a size required for the arithmetic processing in the main scanning direction, and performing a data shifting by one storage region from the one end to the other end each time arithmetic processing is performed in each line;

a first input unit to input unit data one piece by one piece from each line of the unprocessed image data to a storage region at the one end as an input end of an intermediate storage unit corresponding to a line in each arithmetic processing;

an output unit to read and output unit data stored in a storage region at each position determined according to a positional relationship between the target unit data and the reference unit data of the target unit data from each intermediate storage unit; and

a processing execution unit to execute arithmetic processing with a use of unit data output from the output unit.

12. The image processing apparatus according to claim 11 , further comprising:

a first memory to store the unprocessed image data;

a second memory to store a processing result of the processing execution unit as processed data; and

a second input unit,

wherein the processing execution unit uses processed data of unit data located before target unit data in a scanning order and in the close proximity to the target unit data as the reference unit data,

wherein the first input unit reads one piece of target unit data from the first memory and inputs the target unit data to a storage region at an input end of a prescribed intermediate storage unit in each arithmetic processing,

wherein the second input unit reads processed data in a line containing unit data required for the arithmetic processing and being different from a line containing the target unit data one piece by one piece from the second memory and inputs the processed data to a storage region at an input end of an intermediate storage unit corresponding to the line and being different from the prescribed intermediate storage unit in each arithmetic processing, and

wherein, upon each completion of the arithmetic processing, the processing execution unit outputs a processing result to the second memory and inputs the processing result to a storage region adjacent to the storage region at the input end of the prescribed intermediate storage unit after the data shifting of the intermediate storage unit is performed.

13. The image processing apparatus according to claim 11 , wherein the intermediate storage unit comprises a buffer.

14. The image processing apparatus according to claim 12 , wherein the intermediate storage unit comprises a buffer.

15. The image processing apparatus according to claim 11 , wherein the intermediate storage unit comprises a shift register.

16. The image processing apparatus according to claim 12 , wherein the intermediate storage unit comprises a shift register.

17. The image processing apparatus according to claim 11 , wherein the unit data comprises data of one pixel.

18. The image processing apparatus according to claim 12 , wherein the unit data comprises data of one pixel.

19. The image processing apparatus according to claim 11 , wherein a capacity of each intermediate storage unit is a sum of a distance between two most distant pieces of unit data located in the same line and required for a one-time arithmetic processing, and a double of the prescribed size of unit data.

20. The image processing apparatus according to claim 12 , wherein

a capacity of each intermediate storage unit is a sum of a distance between two most distant pieces of unit data located in the same line and required for a one-time arithmetic processing, and a double of the prescribed size of unit data.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Nov 2, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025235/0233 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2007
From: HIGASHI, FUMINORI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 019857/0947 →