Driving circuit and data driver of planar display device
A clock signal, a data signal, and a latch signal are commonly supplied from a controller to a plurality of the data drivers. The data signal and the latch signal are synchronized with the clock signal. In each of the data drivers, an internal latch signal is generated in synchronization with the clock signal in response to the latch signal. Timing of a rising edge of the internal latch signal is independently controlled in each data driver in accordance with position information where each data driver is arranged.
1. A driving circuit of a planar display device, the driving circuit comprising:
a controller configured to output a latch signal; and
a first and a second data driver configured to receive the latch signal,
wherein each of the first and the second driver comprises:
a data register configured to fetch a display data;
a data latch circuit configured to latch the display data from the data register in response to a leading edge of an internal latch signal;
a driver circuit configured to output the display data in response to a trailing edge of the internal latch signal; and
an internal latch signal generation circuit configured to receive the latch signal to generate the internal latch signal,
wherein the internal latch signal generation circuit comprises:
a delay latch signal generator configured to receive the latch signal to generate at least first and second delay latch signals; and
a selector configured to select, based on a select signal, one of the first and second delay latch signals as a signal corresponding to the internal latch signal,
wherein a leading edge of the first delay latch signal is delayed for a first period from a leading edge of the latch signal, and
wherein a leading edge of the second delay latch signal is delayed for a second period from the leading edge of the latch signal, the second period being different from the first period.
2. The driving circuit according to claim 1 , wherein the delay latch signal generator does not delay a trailing edge of the latch signal to generate the first and second delay latch signals.
3. The driving circuit according to claim 1 , wherein a data latch timing of the data latch circuit is different from a data output timing of the driver circuit.
4. A data driver, comprising:
a data register configured to fetch a display data;
a data latch circuit configured to latch the display data from the data register in response to a leading edge of an internal latch signal;
a driver circuit configured to output the display data in response to a trailing edge of the internal latch signal: and
an internal latch signal generation circuit configured to receive a latch signal to generate the internal latch signal,
wherein the internal latch signal generation circuit comprises:
a delay latch signal generator configured to receive the latch signal to generate at least first and second delay latch signals; and
a selector configured to select, based on a select signal, one of the first and second delay latch signals as a signal corresponding to the internal latch signal,
wherein a leading edge of the first delay latch signal is delayed for a first period from a leading edge of the latch signal, and
wherein a leading edge of the second delay latch signal is delayed for a second period from the leading edge of the latch signal, the second period being different from the first period.
5. The data driver according to claim 4 , wherein a data latch timing of the data latch circuit is different from a data output timing of the driver circuit.
6. The data driver according to claim 4 , wherein the delay latch signal generator does not delay a trailing edge of the latch signal to generate the first and second delay latch signals.
7. The driving circuit according to claim 1 , wherein the internal latch signal generation circuit further comprises:
a counter configured to receive a clock signal and a start signal to generate the select signal.
8. The driving circuit according to claim 7 , wherein the start signal includes a pulse with a predetermined pulse width, and
wherein the counter counts the pulse width of the start signal based on the clock signal, and generates the select signal corresponding to a count value.
9. The driving circuit according to claim 8 , wherein the start signal received by the counter in the first data driver comprises a first start signal,
wherein the start signal received by the counter in the second data driver comprises a second start signal, and
wherein a pulse width of the first start signal is different from that of the second start signal.
10. The driving circuit according to claim 4 , wherein the internal latch signal generation circuit further comprises:
a counter configured to receive a clock signal and a start signal to generate the select signal.
11. The driving circuit according to claim 10 , wherein the start signal includes a pulse with a predetermined width, and
wherein the counter counts a pulse width of the start signal based on the clock signal, and generates the select signal corresponding to a count value.
12. The driving circuit according to claim 1 , wherein each of the first data driver and the second data driver independently controls a timing of the internal latch signal.
13. The data driver according to claim 4 , wherein said data driver comprises a plurality of data drivers, each of the plurality of data drivers controlling a timing of the internal latch signal independent of other ones of the data drivers.