Apparatus and method for selectively enabling and disabling a squelch circuit across AHCI and SATA power states

1. A method for controlling a squelch circuit in a Serial Advanced Technology Attachment (SATA) adapter, comprising:

disabling the squelch circuit if the SATA adapter is not in a PHY Ready state, the SATA adapter is in an Advanced Host Controller Interface (AHCI) Listen Mode, and a Low Power Device Detection (LPDD) feature is enabled;

disabling the squelch circuit if the SATA adapter is in said PHY Ready state, no 8b10b error has occurred, and a first time has transpired since the SATA adapter entered said PHY Ready state and a previous 8b10b error occurred; and

enabling the squelch circuit if an 8b10b error has occurred.

2. The method of claim 1 , comprising:

disabling the squelch circuit if the SATA adapter is in a Partial or a Slumber state and a second time has transpired;

disabling the squelch circuit if the SATA adapter is in said AHCI Listen Mode and said LPDD feature is not enabled and said second time has transpired;

enabling the squelch circuit if the SATA adapter is in said Partial or said Slumber state and a third time has transpired; and

enabling the squelch circuit if the SATA adapter is in said AHCI Listen Mode and said LPDD feature is not enabled and said third time has transpired.

3. The method of claim 1 , comprising enabling the squelch circuit if the SATA adapter is about to transmit an Out of Band (OOB) signal.

4. The method of claim 1 , wherein said first time is longer than a gap between Out of Band (OOB) bursts.

5. The method of claim 2 , wherein said second time is shorter than two series of ComWake Out of Band (OOB) bursts plus one ComWake idle period minus a time taken for the squelch circuit to stabilize after the squelch circuit is enabled.

6. The method of claim 2 , wherein said third time is longer than four series of ComInit Out of Band (OOB) bursts and four series of ComInit idle periods.

7. The method of claim 1 , wherein said step of enabling comprises:

detecting an 8b10b error on differential inputs of the SATA adapter while the squelch circuit is disabled; and

enabling the squelch circuit, wherein a fourth time between when said 8b10b error is detected and when the squelch circuit stabilizes after the squelch circuit is enabled is no more than two consecutive Out of Band (OOB) bursts.

8. The method of claim 1 , wherein the squelch circuit comprises an OOB detector.

9. A Serial Advanced Technology Attachment (SATA) adapter, comprising:

a squelch circuit;

an 8b10b error detector for detecting 8b10b errors;

a first timer having a first time, wherein said first timer is reinitialized when the SATA adapter enters a PHY Ready state and as long as said 8b10b error detector detects 8b10b errors; and

a squelch circuit controller for disabling said squelch circuit if the SATA adapter is not in a PHY Ready state, the SATA adapter is in an Advanced Host Controller Interface (AHCI) Listen Mode, and a Low Power Device Detection (LPDD) feature is enabled and for disabling said squelch circuit if the SATA adapter is in said PHY Ready state, said 8b10b error detector has not detected any 8b10b errors, and said first timer has expired and enabling said squelch circuit if said 8b10b error detector detects an 8b10b error.

10. The SATA adapter of claim 9 , comprising:

a second timer having a second time and a third time, wherein said second timer is initialized to said second time when the SATA adapter powers up, comes out of reset, or said third time expires and said second timer is initialized to said third time when said second time expires,

wherein said squelch circuit controller is for disabling said squelch circuit if the SATA adapter is in a Partial or a Slumber state and said second time has expired and for disabling said squelch circuit if the SATA adapter is in said AHCI Listen Mode and said LPDD feature is not enabled and said second time has expired and for enabling said squelch circuit if the SATA adapter is in said Partial or said Slumber state and said third time has expired and for enabling said squelch circuit if the SATA adapter is in said AHCI Listen Mode and said LPDD feature is not enabled and said third time has expired.

11. The SATA adapter of claim 9 , wherein said squelch circuit controller is for enabling said squelch circuit if the SATA adapter is about to transmit an Out of Band (OOB) signal.

12. The SATA adapter of claim 9 , wherein said first time is longer than a gap between Out of Band (OOB) bursts.

13. The SATA adapter of claim 10 , wherein said second time is shorter than two series of ComWake Out of Band (OOB) bursts plus one ComWake idle period minus a time taken for the squelch circuit to stabilize after the squelch circuit is enabled.

14. The SATA adapter of claim 10 , wherein said third time is longer than four series of ComInit Out of Band (OOB) bursts and four series of ComInit idle periods.

15. The SATA adapter of claim 9 , wherein a fourth time between when said 8b10b error detector detects an 8b10b error and when said squelch circuit stabilizes after said squelch circuit is enabled is no more than two consecutive Out of Band (OOB) bursts.

16. The SATA adapter of claim 9 , wherein said squelch circuit comprises an Out of Band (OOB) detector.