Active load with adjustable common-mode level
View Patent ↗A differential preamplifier includes an active load with adjustable common-mode output level. The active load includes a transistor pair, a resistor pair, and a current source. The transistor load is employed to provide high gain, low offset, and a large bandwidth for the differential preamplifier. The resistor pair and current source are used to increase the common-mode output level of the differential preamplifier and to bias the transistor load. The current source can be varied to provide an adjustable common-mode output level suitable for driving next stage devices. The active load design allows the differential preamplifier to operate using only low power voltage supplies and with small-sized transistors.
1. A differential circuit, comprising:
an active load that provides a differential output signal at respective output terminals of the active load; and
a bias circuit that provides bias to the active load, and configured to provide an adjustable common-mode voltage at the respective output terminals of the active load.
2. The differential circuit of claim 1 , wherein the active load includes a transistor pair having their gates connected together at a common node, the bias circuit further comprising:
a current source coupled to the common node;
a first resistor coupled between a gate and a drain of a first transistor of the transistor pair, and a second resistor coupled between a gate and a drain of a second transistor of the transistor pair.
3. The differential circuit of claim 2 , wherein the current source is determined so that respective voltage drops across the first and second resistors provide a desired common-mode voltage at the output terminals of the active load.
4. The differential circuit of claim 3 , wherein the current source is determined so that respective voltage drops across the first and second resistors place the transistor pair in saturation.
5. The differential circuit of claim 3 , wherein the current source is determined by a feedback loop system coupled to the output terminals of the active load.
6. The differential circuit of claim 5 , wherein the feedback loop system monitors the common-mode voltage at the output terminals of the active load and generates an output signal to adjust the current source.
7. The differential circuit of claim 1 , wherein the transistor pair in the active load is a PMOS transistor pair.
8. A differential circuit, comprising:
a first transistor pair; and
an active load, coupled to the first transistor pair, including:
a second transistor pair having differential output terminals; and
a bias circuit that provides bias voltages to the second transistor pair, and configured to provide an adjustable common-mode voltage at the respective output terminals of the active load.
9. The differential circuit of claim 8 , wherein the second transistor pair has their gates connected together at a common node, the bias circuit further comprising:
a current source coupled to the common node;
a first resistor coupled between a gate and a drain of a first transistor of the second transistor pair, and a second resistor coupled between a gate and a drain of a second transistor of the second transistor pair.
10. The differential circuit of claim 8 , wherein the current source is determined so that respective voltage drops across the first and second resistors provide a desired common-mode voltage at the output terminals of the active load.
11. The differential circuit of claim 10 , wherein the current source is determined so that respective voltage drops across the first and second resistors place the second transistor pair in saturation.
12. The differential circuit of claim 10 , wherein the current source is determined by a feedback loop system coupled to the output terminals of the active load.
13. The differential circuit of claim 12 , wherein the feedback loop system monitors the common-mode voltage at the output terminals of the active load and generates an output signal to adjust the current source.
14. The differential circuit of claim 8 , wherein the first transistor pair is a NMOS transistor pair and the second transistor pair is a PMOS transistor pair.
15. The differential circuit of claim 1 , wherein the differential circuit is a differential amplifier.
16. The differential circuit of claim 8 , wherein the differential circuit is a differential amplifier.
17. A differential circuit, comprising:
a first stage configured to receive a differential input signal; and
a second stage, coupled to an output of the first stage, including:
an active load having a transistor pair that provides a differential output signal at respective output terminals of the active load; and
means for providing an adjustable common-mode voltage at the respective output terminals of the active load.
18. The differential circuit of claim 17 , wherein said means for providing an adjustable common-mode voltage at the respective output terminal includes a means for providing bias voltages to the transistor pair.