Post passivation interconnection schemes on top of the IC chips
View Patent ↗A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
1. A chip comprising:
a silicon substrate;
an ESD circuit in or on said silicon substrate;
a first internal circuit in or on said silicon substrate;
a driver, receiver or I/O circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit;
a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said first internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises nitride;
a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure;
a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure;
a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, and wherein said first terminal is connected to said first internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure;
a third via over said silicon substrate and in said dielectric layer, wherein said third via is connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit; and
a fourth via in said passivation layer and directly over said third via, wherein said fourth via is connected to said third via.
2. The chip of claim 1 further comprising a second internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said second interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.
3. The chip of claim 2 further comprising a third internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said third internal circuit, and a fifth via in said passivation layer, wherein said fifth via is connected to said third and fourth interconnecting structures, wherein said first and second internal circuits are connected to said third internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said fifth via and said fourth interconnecting structure, and wherein said first terminal is connected to said third internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said fifth via and said fourth interconnecting structure.
4. The chip of claim 1 further comprising a second internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said second internal circuit, and a fifth via in said passivation layer, wherein said fifth via is connected to said third and fourth interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said fifth via and said fourth interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said fifth via and said fourth interconnecting structure.
5. The chip of claim 1 , wherein said third and fourth vias provide an access to an external clock for said ESD circuit and for said second terminal.
6. The chip of claim 1 , wherein said third and fourth vias provide an access to an external signal for said ESD circuit and for said second terminal.
7. A chip comprising:
a silicon substrate;
an ESD circuit in or on said silicon substrate;
a first internal circuit in or on said silicon substrate;
a driver, receiver or I/O circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit;
a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said first internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises nitride;
a polymer layer over said passivation layer;
a first via in said polymer layer, wherein said first via is connected to said first interconnecting structure;
a second via in said polymer layer, wherein said second via is connected to said second interconnecting structure;
a third interconnecting structure in said polymer layer and over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, and wherein said first terminal is connected to said first internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure;
a third via over said silicon substrate and in said dielectric layer, wherein said third via is connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit; and
a fourth via in said polymer layer and directly over said third via, wherein said fourth via is connected to said third via.
8. The chip of claim 7 further comprising a second internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said second interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.
9. The chip of claim 8 further comprising a third internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said third internal circuit, and a fifth via in said polymer layer, wherein said fifth via is connected to said third and fourth interconnecting structures, wherein said first and second internal circuits are connected to said third internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said fifth via and said fourth interconnecting structure, and wherein said first terminal is connected to said third internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said fifth via and said fourth interconnecting structure.
10. The chip of claim 7 further comprising a second internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said second internal circuit, and a fifth via in said polymer layer, wherein said fifth via is connected to said third and fourth interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said fifth via and said fourth interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said fifth via and said fourth interconnecting structure.
11. The chip of claim 7 , wherein said third and fourth vias provide an access to an external clock for said ESD circuit and for said second terminal.
12. The chip of claim 7 , wherein said third and fourth vias provide an access to an external signal for said ESD circuit and for said second terminal.
13. A chip comprising:
a silicon substrate;
an ESD circuit in or on said silicon substrate;
a driver, receiver or I/O circuit in or on said silicon substrate;
a first internal circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first interconnecting structure in said dielectric layer and over said silicon substrate, wherein said first interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit;
a second interconnecting structure in said dielectric layer and over said silicon substrate, wherein said second interconnecting structure is connected to said first internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises nitride;
a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure;
a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure;
a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, and wherein said first terminal is connected to said first internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure; and
an external connection point connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit, wherein said driver, receiver or I/O circuit is connected in series between said first interconnecting structure and said external connection point, and wherein said ESD circuit is connected, in parallel with said driver, receiver or I/O circuit, to said external connection point.
14. The chip of claim 13 further comprising a second internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said second interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.
15. The chip of claim 14 further comprising a third internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said third internal circuit, wherein said first and second internal circuits are connected to said third internal circuit through said second interconnecting structure, and wherein said first terminal is connected to said third internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.
16. The chip of claim 14 further comprising a third internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said third internal circuit, and a third via in said passivation layer, wherein said third via is connected to said third and fourth interconnecting structures, wherein said first and second internal circuits are connected to said third internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, and wherein said first terminal is connected to said third internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said third via and said fourth interconnecting structure.
17. The chip of claim 13 further comprising a second internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said second internal circuit, and a third via in said passivation layer, wherein said third via is connected to said third and fourth interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said third via and said fourth interconnecting structure.
18. The chip of claim 13 , wherein said external connection point provides an access to an external clock for said ESD circuit and for said second terminal.
19. The chip of claim 13 , wherein said external connection point provides an access to an external signal for said ESD circuit and for said second terminal.
20. The chip of claim 13 further comprising a polymer layer over said passivation layer, wherein said third interconnecting structure is in said polymer layer.