Semiconductor device and method for manufacturing the same
View Patent ↗It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si<31/12 above the first gate insulating film, and a second nickel silicide having a composition of Ni/Si≧31/12 on the second gate insulating film; and segregating aluminum at an interface between the first nickel silicide and the first gate insulating film by diffusing aluminum through the first nickel silicide.
1. A method for manufacturing a semiconductor device, comprising:
forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate;
forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively;
forming a first and second gate electrodes on the first and second gate insulating films respectively, the first gate electrode including a first nickel silicide having a composition of Ni/Si<31/12, and the second gate electrode including a second nickel silicide having a composition of Ni/Si≧31/12;
forming an aluminum layer on the first and second gate electrodes; and
diffusing the aluminum through the first gate electrode and diffusing the aluminum in the second gate electrode by performing heat treatment, to segregate the aluminum at an interface between the first gate electrode and the first gate insulating film.
2. The method according to claim 1 , wherein the forming the first and second gate electrodes includes:
forming first and second silicon layers above the first and second gate insulating films, respectively;
forming a third silicon layer by thinning the second silicon layer;
forming nickel layers of the same film thickness on the first silicon layer and the third silicon layer; and
causing solid phase reactions between the nickel layer and the first silicon layer and between the nickel layer and the third silicon layer by performing heat treatment.
3. The method according to claim 1 , wherein the forming the first and second gate electrodes includes:
forming first and second silicon layers above the first and second gate insulating films, respectively;
forming first and second silicon germanium compound layers on the first and second silicon layers, respectively;
selectively removing the first and second silicon germanium compound layers;
forming a third silicon layer by thinning the second silicon layer;
forming nickel layers of the same film thickness on the first silicon layer and the third silicon layer; and
causing solid phase reactions between the nickel layer and the first silicon layer and between the nickel layer and the third silicon layer by performing heat treatment.
4. The method according to claim 1 , wherein the forming the first and second gate electrodes includes:
forming first and second silicon layers above the first and second gate insulating films, respectively;
forming a first nickel layer on the first and second silicon layers;
forming the first nickel silicide by causing solid phase reactions between the first nickel layer and the first silicon layer and between the first nickel layer and the second silicon layer through heat treatment;
forming a second nickel layer on the first nickel silicide located above the n-type semiconductor region; and
turning at least a part of the first nickel silicide located above the n-type semiconductor region into the second nickel silicide by performing heat treatment.
5. The method according to claim 4 , further comprising:
forming a layer containing one of titanium, zirconium, and hafnium on the first nickel silicide above the n-type semiconductor region, the forming the layer being carried out between the forming the first nickel silicide and the forming the second nickel layer.
6. The method according to claim 4 , wherein the turning at least a part of the first nickel silicide into the second nickel silicide includes turning all the nickel silicide located above the n-type semiconductor region into the second nickel silicide.
7. The method according to claim 1 , wherein
the aluminum segregated at the interface between the first gate electrode and the first gate insulating film has a thickness of one atomic layer or greater and
the aluminum segregated at an interface between the second gate electrode and the second gate insulating film has a thickness thinner than one atomic layer.
8. A method for manufacturing a semiconductor device, comprising:
forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate;
forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively;
forming a first and second gate electrodes on the first and second gate insulating films respectively, the first gate electrode including a first nickel silicide made of one of NiSi 2 cubic, NiSi orthorhombic, and Ni 2 Si orthorhombic, and the second gate electrode including a second nickel silicide made of at least one of Ni 31 Si 12 hexagonal and Ni 3 Si cubic;
forming an aluminum layer on the first and second gate electrodes; and
by performing heat treatment, diffusing the aluminum through the first gate electrode and diffusing the aluminum in the second gate electrode, to segregate the aluminum at an interface between the first gate electrode and the first gate insulating film.
9. The method according to claim 8 , wherein the forming the first and second gate electrodes includes:
forming first and second silicon layers above the first and second gate insulating films, respectively;
forming a third silicon layer by thinning the second silicon layer;
forming nickel layers of the same film thickness on the first silicon layer and the third silicon layer; and
causing solid phase reactions between the nickel layer and the first silicon layer and between the nickel layer and the third silicon layer by performing heat treatment.
10. The method according to claim 8 , wherein the forming the first and second gate electrodes includes:
forming first and second silicon layers above the first and second gate insulating films, respectively;
forming first and second silicon germanium compound layers on the first and second silicon layers, respectively;
selectively removing the first and second silicon germanium compound layers;
forming a third silicon layer by thinning the second silicon layer;
forming nickel layers of the same film thickness on the first silicon layer and the third silicon layer; and
causing solid phase reactions between the nickel layer and the first silicon layer and between the nickel layer and the third silicon layer by performing heat treatment.
11. The method according to claim 8 , wherein the forming the first and second gate electrodes includes:
forming first and second silicon layers above the first and second gate insulating films, respectively;
forming a first nickel layer on the first and second silicon layers;
forming the first nickel silicide by causing solid phase reactions between the first nickel layer and the first silicon layer and between the first nickel layer and the second silicon layer through heat treatment;
forming a second nickel layer on the first nickel silicide located above the n-type semiconductor region; and
turning at least a part of the first nickel silicide located above the n-type semiconductor region into the second nickel silicide by performing heat treatment.
12. The method according to claim 11 , further comprising:
forming a layer containing one of titanium, zirconium, and hafnium on the first nickel silicide above the n-type semiconductor region, the forming the layer being carried out between the forming the first nickel silicide and the forming the second nickel layer.
13. The method according to claim 11 , wherein the turning at least a part of the first nickel silicide into the second nickel silicide includes turning all the nickel silicide located above the n-type semiconductor region into the second nickel silicide.
14. The method according to claim 8 , wherein
the aluminum segregated at the interface between the first gate electrode and the first gate insulating film has a thickness of one atomic layer or greater; and
the aluminum segregated at an interface between the second gate electrode and the second gate insulating film has a thickness thinner than one atomic layer.
15. The method according to claim 1 , wherein the aluminum is diffused through the nickel silicide in the first gate electrode.
16. The method according to claim 1 , wherein the decreasing rate in the depth direction of the aluminum profile in the second gate electrode was larger than that in the first gate electrode.
17. The method according to claim 8 , wherein the aluminum is diffused through the nickel silicide in the first gate electrode.
18. The method according to claim 8 , wherein the decreasing rate in the depth direction of the aluminum profile in the second gate electrode was larger than that in the first gate electrode.