Semiconductor memory with a delay circuit
View Patent ↗A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
1. A semiconductor device comprising a delay circuit, the delay circuit comprising:
at least one circuit unit comprising:
an inverter including:
a first MOS transistor having a source thereof connected to a first power supply; and
a second MOS transistor having a source thereof connected to a second power supply, having a gate thereof connected in common with a gate of said first MOS transistor to an input terminal, and having a drain thereof connected in common with a drain of said first MOS transistor to an output terminal, said second MOS transistor having a different conductivity type from a conductivity type of said first MOS transistor;
a resistor having one terminal thereof connected to said output terminal of said inverter; and
a MOS capacitor connected between the other terminal of said resistor and said first or second power supply,
the delay circuit having a characteristic in which a delay time thereof decreases more when a provided power supply voltage is low than when the provided power supply voltage is high.
2. A memory device, comprising:
a memory cell array including a plurality of memory cells;
a driver for driving a word line coupled to the selected memory cell;
a first control circuit for generating a control signal to control said driver; and
a sense amplifier for amplifying a voltage on a bit line coupled to the selected memory cell;
wherein said first control circuit has a first delay characteristic in which the higher a power supply voltage applied to the first control circuit becomes, the larger a delay time of the first control circuit becomes, while said sense amplifier has a second delay characteristic in which the higher a power supply voltage applied to said sense amplifier becomes, the smaller a delay time of the circuit becomes.
3. A memory device, comprising:
a memory cell array including a plurality of memory cells; and
a first control circuit for accessing a selected memory cell;
said first control circuit having a first delay characteristic in which the higher a power supply voltage applied to the first control circuit becomes, the larger a delay time of the first control circuit becomes.
4. The memory device according to claim 3 , further comprising
a second control circuit for accessing the selected memory cell;
said second control circuit having a second delay characteristic in which the higher a power supply voltage applied to the second control circuit becomes, the smaller a delay time of the second control circuit becomes.