Circuit designing program and circuit designing system having function of test point insertion

1. A computer program storage device storing a circuit design program to cause a computer to execute a circuit design process, comprising:

(A) referring to a netlist of a circuit to extract a plurality of equivalent faults f j keeping a mutually equivalent relation from all stuck-at faults possible to occur in the circuit;

(B) searching a number n(f j ) of test points required for a number of an equivalent fault keeping an equivalent relation with a search object equivalent fault f j with each of the plurality of equivalent faults as the search object equivalent fault to become a predetermined number and an insertion position G(f j );

(C) calculating a probability p(f j ) of a single stuck-at fault being included in a set of equivalent faults including at least the search object equivalent fault f j at an occasion when the stuck-at fault takes place in the circuit;

(D) calculating a parameter e(f j ) derived by an equation: e(f j )=p(f j )/n(f j ) on each pattern of the insertion position G(f j );

(E) determining the insertion position G(f max ) giving a maximum value among the calculated parameters e(f j ) as a position where the test point is inserted; and

(F) respectively inserting the n(f max ) test points into the determined insertion position G(f max ).

2. The storage device according to claim 1 , wherein:

the predetermined number is 1; and

in the (B) step, a number n(f j ) of test points required for the search object equivalent fault f j to become an independent fault, and the insertion position G(f j ), are searched.

3. The storage device according to claim 2 , wherein:

the circuit design process further includes (H) extracting a set Fs(f j ) of the equivalent fault f j to become an independent fault concurrently at an occasion when the test point is inserted into the insertion position G(f j ) for the search object equivalent fault f j ; and

in the (C) step, a probability of the single stuck-at fault being included in the set Fs(f j ) is calculated as the probability p(f j ).

4. The storage device according to claim 1 , wherein:

the predetermined number is an integer of not less than 2;

N equivalent faults are referred to as an independent fault group in the case where the N equivalent faults are positioned at mutually adjacent nodes and are devoided of the equivalent relation with other faults; and

in the (B) step, a number n(f j ) of test points required for the search object equivalent fault f j to become an element of an independent fault group, and the insertion position G(f j ), are searched.

5. The storaae device according to claim 4 , wherein:

the circuit design process further includes (I) extracting a set Fs(f j ) of the equivalent fault f j to become an element of an independent fault group concurrently at an occasion when the test point is inserted into the insertion position G(f j ) for the search object equivalent fault f j ; and

in the (C) step, probability of the single stuck-at fault being included in the set Fs(f j ) is calculated as the probability p(f j ).

6. The storage device according to claim 4 , wherein the integer N is 2.

7. The storage device according to claim 1 , wherein

in the (C) step, a probability of the single stuck-at fault corresponding with the search object equivalent fault f j is calculated as the probability p(f j ).

8. A circuit design system, comprising:

a storage that stores a netlist of a circuit;

an equivalent fault extraction unit that refers to the netlist to extract a plurality of equivalent faults f j keeping a mutually equivalent relation from all stuck-at faults possible to occur in the circuit;

an insertion position searching unit that searches a number n(f j ) of test points required for a number of equivalent fault keeping an equivalent relation with a search object equivalent fault f j with each of the plurality of equivalent faults as the search object equivalent fault to become a predetermined number, and an insertion position G(f j );

a fault probability calculation unit that calculates a probability p(f j ) of a single stuck-at fault being included in a set of equivalent faults including at least the search object equivalent fault f j at an occasion when the stuck-at fault takes place in the circuit;

a determination unit that calculates a parameter e(f j ) derived by an equation: e(f j )=p(f j )/n(f j ) on each pattern of the insertion position G(f j ) and searching the insertion position G(f max ) giving a maximum value among the calculated parameters e(f j ); and

a test point insertion unit respectively inserting the n(f max ) test points into the insertion position G(f max ).

9. The circuit design system according to claim 8 , wherein:

the predetermined number is 1; and

the insertion position searching unit searches a number n(f j ) of test points required for the search object equivalent fault f j to become an independent fault and the insertion position G(f j ).

10. The circuit design system according to claim 9 , further comprising:

an independent fault extraction unit that extracts a set Fs(f j ) of the equivalent fault f j to become an independent fault concurrently at an occasion when the test point is inserted into the insertion position G(f j ) for the search object equivalent fault f j , wherein

the fault probability calculation unit calculates a probability of the single stuck-at fault being included in the set Fs(f j ) as the probability p(f j ).

11. The circuit design system according to claim 8 , wherein:

the predetermined number is an integer of not less than 2;

N equivalent faults are referred to as an independent fault group in the case where the N equivalent faults are positioned at mutually adjacent nodes and are devoid of the equivalent relation with other faults; and

the insertion position searching unit searches a number n(f j ) of test points required for the search object equivalent fault f j to become an element of the independent fault group and an insertion position G(f j ).

12. The circuit design system according claim 11 , further comprising:

an independent fault extraction unit that extracts a set Fs(fhd j) of the equivalent fault f j to become an element of an independent fault group concurrently at an occasion when the test point is inserted into the insertion position G(f j ) for the search object equivalent fault f j , wherein

the fault probability calculation unit calculates a probability of the single stuck-at fault being included in the set Fs(f j ) as the probability p(f j ).

13. The circuit design system according to claim 11 , wherein

the predetermined number is 2.

14. The circuit design system according to claim 8 , wherein

the fault probability calculation unit calculates a probability of the single stuck-at fault corresponding with the search object equivalent fault f j as the probability p(f j ).

15. A method of executing a circuit design process, comprising:

using a computer to perform:

(A) referring to a netlist of a circuit to extract a plurality of equivalent faults f j keeping a mutually equivalent relation from all stuck-at faults possible to occur in the circuit;

(B) searching a number n(f j ) of test points required for a number of an equivalent fault keeping an equivalent relation with a search object equivalent fault f j with each of the plurality of equivalent faults as the search object equivalent fault to become a predetermined number and an insertion position G(f j );

(C) calculating a probability p(f j ) of a sinale stuck-at fault being included in a set of equivalent faults including at least the search object equivalent fault f j at an occasion when the stuck-at fault takes place in the circuit;

(D) calculating a parameter e(f j ) derived by an equation: e(f j )=p(f j )/n(f j ) on each pattern of the insertion position G(f j );

(E) determining the insertion position G(f max ) giving a maximum value among the calculated parameters e(f j ) as a position where the test point is inserted; and

(F) respectively inserting the n(f max ) test points into the determined insertion position G(f max ).