MOSFET with temperature sense facility
View Patent ↗A transistor ( 1 ) has a FET ( 2 ) and a temperature sensing diode ( 4 ) integrated within it. Gate drive circuit ( 12 ) is arranged to switch off FET ( 2 ) and in this case biasing circuit ( 14 ) drives a constant current through the diode ( 4 ). The voltage across the diode ( 4 ) is measured by voltage sensor ( 15 ) which provides a measure of the temperature of the FET.
1. A transistor device, comprising: a field effect transistor (FET) on a substrate with source, gate and drain; a gate bond pad on a first major surface of the substrate; at least one temperature sensing diode; and a channel between the gate bond pad and the temperature sensing diode, the temperature sensing diode being electrically connected between the gate and source of the FET, the temperature sensing diode being oriented with the diode cathode connected to the gate of the FET and the diode anode connected to the source of the FET.
2. A transistor device according to claim 1 wherein the temperature sensing diode is a zener diode.
3. A transistor device according to claim 1 wherein the gate bond pad is located in a region of the first major surface surrounded by the FET.
4. A transistor circuit, comprising: a transistor device including a field effect transistor (FET) with source, gate and drain and a temperature sensing diode connected between the gate and source of the FET, the diode cathode connected to the gate of the FET and the diode anode connected to the source of the FET; a biasing circuit arranged to apply a negative bias to the FET gate when the FET is off; and a sensor connected between the gate and source of the FET to measure a parameter of the temperature sensing diode, the parameter representing the temperature of the FET when the FET is off.
5. A transistor circuit according to claim 4 wherein the biasing circuit includes a constant current source and the sensor is a voltage sensor.
6. A transistor circuit according to claim 4 wherein the temperature sensing diode is under the gate bond pad of the FET.
7. A transistor circuit according to claim 4 comprising; a plurality of devices each with temperature sensing diodes connected between the gate and source of a respective FET, the diode cathode connected to the gate of the FET and the diode anode connected to the source of the FET; and a sensor connected to the gate of each FET to measure a parameter representing the temperature of the FET wherein the biasing circuit is arranged to apply a negative bias to each FET gate when the respective FET is off.
8. A transistor circuit according to claim 7 wherein the FETs are arranged in parallel to drive a circuit load and a gate drive circuit is arranged to switch off the FETs alternately.
9. A method of monitoring the temperature of a FET having a temperature sensing diode connected between the gate and source of the FET, the diode cathode being connected to the gate of the FET and the diode anode being connected to the source of the FET, the method comprising:
controlling the gate of the FET to turn off the FET;
applying a negative bias to the FET gate when the FET is turned off;
determining a value of a parameter of the temperature sensing diode, the value representing the temperature of the FET when the FET is off; and
controlling the gate of the turned off FET to turn the FET on again.
10. A method according to claim 9 further comprising determining from the value of the parameter whether the temperature of the FET is above a predetermined target value, then controlling the gate of the turned off FET to keep the FET switched off until the temperature reduces to the predetermined target value.
11. A method according to claim 9 wherein a plurality of FETs are arranged in parallel to drive a circuit load connected between source and drain, each FET having a temperature sensing diode connected between the gate and source, the diode cathode connected to the gate of the FET and the diode anode connected to the source of the FET, wherein controlling the gate of the FET includes switching off the FET gates alternately.