Method of manufacturing a semiconductor device having a buried doped region
View Patent ↗A method of providing a region of doped semiconductor ( 40 ) which is buried below the surface of a semiconductor substrate ( 10 ) without the requirement of epitaxially deposited layers is provided. The method includes the steps of forming first and second trench portions ( 26,28 ) in a semiconductor substrate and then introducing dopant ( 100 ) into the trench portions and diffusing the dopant into the semiconductor substrate such that a region of doped semiconductor ( 40 ) is formed extending from the first trench portion to the second trench portion. A diffusion barrier, for example formed of two barrier trenches ( 16, 18 ), is provided in the substrate adjacent the doping trenches to inhibit lateral diffusion of dopant from the doping trenches so as to maintain an undoped region ( 30 ) above the region of doped semiconductor. Advantageously, the electrical properties of the buried layer can be adjusted by varying the depths and size/spacing of the doping trenches and diffusion barrier(s), and the doping and diffusion parameters. The doping trenches can later be filled with polysilicon to provide electrical contact to the buried doped region.
1. A method of providing a region of doped semiconductor below the surface of a semiconductor substrate, the method comprising:
forming first and second trench portions in a semiconductor substrate;
introducing dopant into the trench portions;
forming a diffusion barrier in the semiconductor substrate, the first and second trench portions being deeper than the diffusion barrier;
then diffusing the dopant into the semiconductor substrate such that a region of doped semiconductor is formed extending from the first trench portion to the second trench portion, the diffusion barrier serving to inhibit diffusion of dopant from the first or second trench portions so as to maintain an undoped region above the region of doped semiconductor and;
wherein forming the diffusion barrier includes forming third and fourth trench portions spaced from one another between the first and second trench portions.
2. A method according to claim 1 , further comprising the step of filling the third and fourth trench portions with a dielectric material.
3. A method according to claim 1 , wherein the depths of the third and fourth trench portions are greater than 5 μm.
4. A method according to claim 3 , wherein the depths of the third and fourth trench portions are greater than 10 μm.
5. A method according to claim 1 , wherein the third and fourth trench portions are provided by a single barrier trench which is arranged in a closed-loop.
6. A method according to claim 5 , wherein the single barrier trench is annular.
7. A method according to claim 5 , wherein the single barrier trench is substantially rectangular.
8. A method according claim 7 , wherein the first and second trench portions are provided by a single doping trench which is arranged in a closed-loop.
9. A method according to claim 8 , wherein the single doping trench is annular.
10. A method according to claim 8 , wherein the single doping trench is substantially rectangular.
11. A method according to claim 10 , including the step of filling the first and second trench portions with polysilicon after introducing the dopant therein.
12. A method according to claim 11 , wherein the semiconductor substrate comprises n-type or p-type doped silicon and wherein the dopant introduced into the trench portions is of the opposite conductivity type to that of the substrate.
13. An integrated circuit device comprising a region of doped semiconductor which is buried below the surface of a semiconductor substrate and fabricated according to claim 12 .