Semiconductor device and its manufacturing method, semiconductor manufacturing mask, and optical proximity processing method

1. A mask for semiconductor manufacture, for use in manufacturing a semiconductor device which includes a logic circuit, wherein

a mask area corresponding to said logic circuit includes:

a first area which is subjected to optical proximity correction with predetermined, accuracy; and

a second area which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy;

said first area includes a gate interconnection line which acts as transistor, and

said second area includes a dummy layout pattern which does not act as a transistor.

2. A manufacturing method of a mask for manufacturing a semiconductor device which includes a logic circuit, comprising the steps of:

(a) inputting a design layout of said logic circuit to a predetermined data base;

(b) classifying said design layout of said logic circuit to said data base into a first area of predetermined accuracy and a second area of accuracy lower than said predetermined accuracy according to accuracy required to an optical proximity effect;

(c) making first optical proximity correction (OPC) on said first area in the design layout of said logic circuit with said predetermined accuracy;

(d) making second optical proximity correction on said second area in the design layout of said logic circuit with accuracy lower than said predetermined accuracy, and

(e) writing on a mask based on a post-OPC layout obtained in steps (c) and (d), wherein

said first area includes a gate interconnection line which acts as a transistor, and

said second area includes a dummy layout pattern which does not act as a transistor.

3. The manufacturing method of a mask according to claim 2 , wherein

in said step (d), said second optical proximity correction is made by application of a uniform bias.

4. The manufacturing method of a mask according to claim 2 , wherein

in said step (d), said second optical proximity correction is made by processing edge positions with said predetermined accuracy without edge segmentation.

5. The manufacturing method of a mask according to claim 2 , wherein

in said step (d), said second optical proximity correction is made by edge segmentation with accuracy lower than said predetermined accuracy.

6. The manufacturing method of a mask according to claim 2 , wherein

in said step (d), said second optical proximity correction is made by simplifying rule-based OPC specifications.

7. The manufacturing method of a mask according to claim 2 , wherein

in said step (d), said second optical proximity correction is made by reducing model-based OPC specifications.

8. The manufacturing method of a mask according to claim 2 , wherein

in said step (d), said second optical proximity correction is made by merging a plurality of kinds of patterns which are similar to each other in shape, into one kind of pattern.

9. The manufacturing method of a mask according to claim 2 , wherein

in said step (d), said second optical proximity correction is made by replacing a predetermined design layout by a previously registered post-OPC layout.

10. The manufacturing method of a mask according to claim 9 , wherein

in said step (d), said second optical proximity correction is made according to the types of design layouts located around said predetermined design layout.

11. The manufacturing method of a mask according to claim 9 , wherein

said second proximity correction is also made on a boundary portion around said predetermined design layout.

12. The manufacturing method of a mask according to claim 2 , wherein said step (c) is performed after said step (d).

13. A method of manufacturing a semiconductor device including a logic circuit, comprising the steps of:

(a) generating a first layout of said logic circuit on a mask by exposure with predetermined accuracy, using a post-OPC layout of said logic circuit;

(b) generating a second layout of said logic circuit on the mask by exposure with accuracy lower than said predetermined accuracy, using the post-OPC layout of said logic circuit;

using a photomask produced from post-OPC layout patterns obtained in steps (a) and (b), transferring said layout patterns on a photoresist-coated semiconductor substrate; and

processing a wafer according to said layout patterns transferred, wherein

said first area includes a gate interconnection line which acts as a transistor, and

said second area includes a dummy layout pattern which does not act as a transistor.

14. A method of manufacturing a semiconductor device including a logic circuit, comprising the steps of:

(a) generating a first layout of said logic circuit on a wafer by exposure with predetermined accuracy, using a post-OPC layout of said logic circuit;

(b) generating a second layout of said logic circuit on the wafer by exposure with accuracy lower than said predetermined accuracy, using the post-OPC layout of said logic circuit; and

processing said wafer according to layout patterns written from post-OPC layout patterns obtained in said steps (a) and (b), wherein

said first area includes a gate interconnection line which acts as a transistor, and

said second area includes a dummy layout pattern which does not act as a transistor.

15. A manufacturing method of a semiconductor device which includes a logic circuit, comprising the steps of

(a) inputting a design layout of said logic circuit to a predetermined data base;

(b) classifying said design layout of said logic circuit to said data base into a first area of predetermined accuracy and a second area of accuracy lower than said predetermined accuracy according to accuracy required to an optical proximity effect;

(c) making first optical proximity correction (OPC) on said first area in the design layout of said logic circuit with said predetermined accuracy;

(d) making second optical proximity correction on said second area in the design layout of said logic circuit with accuracy lower than said predetermined accuracy, and

(e) directly writing on a photoresist-coated semiconductor substrate, using post-OPC layout patterns which were obtained in steps (a) and (b) and which were laid out in storage means in a direct imaging device; and

(f) processing a wafer according to said layout patterns written, wherein

said first area includes a gate interconnection line which acts as a transistor, and

said second area includes a dummy layout pattern which does not act as a transistor.

16. The manufacturing method of a semiconductor device according to claim 15 , wherein

said step (c) is performed after said step (d).

17. The manufacturing method of a semiconductor device according to claim 15 , wherein

in said step (d), said second optical proximity correction is made by application of a uniform bias.

18. The manufacturing method of a semiconductor device according to claim 15 , wherein

in said step (d), said second optical proximity correction is made by processing edge positions with said predetermined accuracy without edge segmentation.

19. The manufacturing method of a semiconductor device according to claim 15 , wherein

in said step (d), said second optical proximity correction is made by edge segmentation with accuracy lower than said predetermined accuracy.

20. The manufacturing method of a semiconductor device according to claim 15 , wherein

in said step (d), said second optical proximity correction is made by simplifying rule-based OPC specifications.

21. The manufacturing method of a semiconductor device according to claim 15 , wherein

in said step (d), said second optical proximity correction is made by reducing model-based OPC specifications.

22. The manufacturing method of a semiconductor device according to claim 15 , wherein

in said step (d), said second optical proximity correction is made by replacing a predetermined design layout by a previously registered post-OPC layout.

23. The manufacturing method of a semiconductor device according to claim 22 , wherein

in said step (d), said second optical proximity correction is made according to the types of design layouts located around said predetermined design layout.

24. The manufacturing method of a semiconductor device according to claim 22 , wherein

said second proximity correction is also made on a boundary portion around said predetermined design layout.