Field effect transistor
View Patent ↗A field effect transistor ( 100 ) exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode ( 116 ) and a second field plate electrode ( 118 ). The second field plate electrode includes a shielding part ( 119 ) located in the region between the first field plate electrode and a drain electrode ( 114 ), and serves to shield the first field plate electrode from the drain electrode. When in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region where the second field plate electrode ( 118 ) overlap the upper part of a structure including the first field plate electrode and a gate electrode ( 113 ) is designated as Lol, and the gate length is Lg, the relation expressed as 0 ≦Lol/Lg≦1 holds.
1. A field effect transistor, comprising:
a layer structure made of Group III nitride semiconductor comprising hetero-junction;
a source electrode and a drain electrode formed on the layer structure made of Group III nitride semiconductor with a space separating each other;
a gate electrode placed between the source electrode and the drain electrode;
a first field plate placed over the layer structure made of Group III nitride semiconductor in a region between the gate electrode and the drain electrode, and isolated from the layer structure made of Group III nitride semiconductor; and
a second field plate placed over the layer structure made of Group III nitride semiconductor, and isolated from the layer structure made of Group III nitride semiconductor and the first field plate,
wherein the first field plate is biased at the same electric potential as that of the gate electrode, the second field plate is biased at the same electric potential as that of the source electrode, the second field plate comprises a shielding part located in a region between the first field plate and the drain electrode, and serving to shield the first field plate from the drain electrode, and an upper end of the shielding part is located above an upper surface of the first field plate,
whereby, in a cross sectional view in the gate length direction, when a length in a gate length direction of an overlap region where the second field plate overlaps an upper part of a structure comprising the first field plate and the gate electrode is designated as Lol and a gate length is designated as Lg, the relation expressed below is satisfied:
0 <Lol/Lg ≦1;
wherein the field effect transistor further comprises a first insulating film for covering a surface of the layer structure made of Group III nitride semiconductor in the region between the gate electrode and the drain electrode, and
wherein the first insulating film is a film containing nitrogen.
2. The field effect transistor as claimed in claim 1 , wherein the lower end of the shielding part is located nearer to the surface of the layer structure made of Group III nitride semiconductor than the lower end of the first field plate.
3. The field effect transistor as claimed in claim 2 , further comprising:
a first insulating film for covering a surface of the layer structure made of Group III nitride semiconductor in the region between the gate electrode and the drain electrode,
wherein a recessed part is provided at the first insulating film in the region between the first field plate and the drain electrode, and
the first field plate is provided in a manner in contact with a upper surface of the first insulating film, and the lower end of the shielding part is located within the recessed part.
4. The field effect transistor as claimed in claim 1 , wherein the lower end of the first field plate is located nearer to the surface of the layer structure made of Group III nitride semiconductor than the lower end of the shielding part.
5. The field effect transistor as claimed in claim 4 , comprising:
a first insulating film for covering a surface of the layer structure made of Group III nitride semiconductor in the region between the gate electrode and the drain electrode; and
a second insulating film provided on the first insulating film in the region between the first field plate and the drain electrode,
wherein the first field plate is provided in a manner in contact with a upper surface of the first insulating film, and the lower end of the shielding part is in contact with a upper surface of the second insulating film.
6. The field effect transistor as claimed in claim 1 , wherein the first field plate is integrally constructed together with the gate electrode in the monolithic shape.
7. The field effect transistor as claimed in claim 1 , wherein the first field plate comprises an electric field control electrode provided in a manner spaced from the gate electrode.
8. The field effect transistor as claimed in claim 1 , wherein the second field plate shows some overlap with the first field plate, and the second field plate is free from overlapping with the gate electrode.
9. The field effect transistor as claimed in claim 1 , wherein, in a cross sectional view in the gate length direction, when an extension width in the gate length direction of the first field plate from the gate electrode end part toward the drain electrode is designated as Lfp 1 , and a length in the gate length direction of a lower surface of the second field plate is designated as Lfp 2 , the formula (1) expressed below is satisfied:
0.5 ×Lfp 1 ≦Lfp 2 (1).
10. The field effect transistor as claimed in claim 1 , wherein the second field plate is provided in a manner in contact with an insulating film for covering a side surface of the first field plate, whereby the aforementioned structure is constructed in the following structure:
in the cross sectional view in the gate length direction, when an extension width in the gate length direction of the first field plate from the gate electrode end part toward the drain electrode is designated as Lfp 1 ;
a length in the gate length direction of a lower surface of the second field plate is designated as Lfp 2 ;
a distance between the gate electrode and the drain electrode is designated as Lgd; and
a thickness of the insulating film at a side surface of the first field plate is designated as d 3 , the formulas (1) and (2) expressed below are satisfied:
0.5 ×Lfp 1 Lfp 2 (1)
Lfp 1 +Lfp 2 +d 3≦⅗ ×Lgd, (2)
11. The field effect transistor as claimed in claim 1 , wherein there is employed a structure in which, in the cross sectional view in the gate length direction, when a length in the gate length direction of a lower surface of the second field plate is designated as Lfp 2 , and a distance between a lower surface of the second field plate in a region between the first field plate and the gate electrode and the layer structure made of Group III nitride semiconductor is designated as d 2 , the formula (3) expressed below is satisfied:
d 2≦0.5 ×Lfp 2 (3) .
12. The field effect transistor as claimed in claim 7 , wherein the first field plate is free from overlapping with the gate electrode.
13. The field effect transistor as claimed in claim 1 , wherein, in a cross sectional view in the gate length direction, when an extension width in the gate length direction of the first field plate from the gate electrode end part toward the drain electrode is designated as Lfp 1 , the relation expressed below is satisfied:
0 <Lfp 1 /Lg<Lol/Lg ≦1.
14. The field effect transistor as claimed in claim 1 , wherein the relation expressed below is satisfied:
0 <Lol/Lg ≦0.7.
15. A field effect transistor, comprising:
a layer structure made of Group III nitride semiconductor comprising hetero-junction;
a source electrode and a drain electrode formed on the layer structure made of Group III nitride semiconductor with a space separating each other;
a gate electrode placed between the source electrode and the drain electrode;
a first field plate placed over the layer structure made of Group III nitride semiconductor in a region between the gate electrode and the drain electrode, and isolated from the layer structure made of Group III nitride semiconductor; and
a second field plate placed over the layer structure made of Group III nitride semiconductor, and isolated from the layer structure made of Group III nitride semiconductor and the first field plate,
wherein the first field plate is biased at the same electric potential as that of the gate electrode, the second field plate is biased at the same electric potential as that of the source electrode, the second field plate comprises a shielding part located in a region between the first field plate and the drain electrode, and serving to shield the first field plate from the drain electrode, and an upper end of the shielding part is located above an upper surface of the first field plate,
whereby, in a cross sectional view in the gate length direction, when a length in a gate length direction of an overlap region where the second field plate overlaps an upper part of a structure comprising the first field plate and the gate electrode is designated as Lol and a gate length is designated as Lg, the relation expressed below is satisfied:
0 <Lol/Lg ≦1;
wherein each of the source, drain, and gate electrodes being formed on a common surface of the layer structure made of Group III nitride semiconductor.