Silicon germanium heterojunction bipolar transistor structure and method
View Patent ↗Disclosed is a design structure for an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
1. A design structure for a semiconductor structure,
said design structure comprising at least layout parameters, test patterns and other testing information and manufacturing line routing information for said semiconductor structure,
said design structure being embodied in a machine readable storage medium accessible by a machine that processes said design structure to produce said semiconductor structure, and
said semiconductor structure comprising:
a first semiconductor layer having a bottom surface and comprising silicon germanium and a first dopant having a first conductivity type; and
a second semiconductor layer below and immediately adjacent to said first semiconductor layer, said second semiconductor layer comprising silicon; and
a third semiconductor layer below and immediately adjacent to said second semiconductor layer,
none of said first semiconductor layer, said second semiconductor layer and said third semiconductor layer being carbon-doped,
said second semiconductor layer having a top surface adjacent to said bottom surface and comprising a diffusion region at said top surface,
said diffusion region comprising both said first dopant and a second dopant having a second conductivity type different from said first conductivity type, and
said top surface comprising approximately no defects such that a peak concentration of said first dopant in said first semiconductor layer adjacent to said bottom surface is at least 100 times greater than a concentration of said first dopant in said diffusion region of said second semiconductor layer.
2. The design structure according to claim 1 , said design structure comprising a netlist which describes a circuit.
3. The design structure according to claim 1 , said design structure residing on a storage medium as a data format used for the exchange of layout data of integrated circuits.
4. The design structure according to claim 1 , said design structure comprising at least one of test data files, characterization data, verification data, and design specifications.
5. The design structure according to claim 1 , said peak concentration of said first dopant in said first semiconductor layer being greater than approximately 1×10 19 cm −3 at approximately 0.03 μm above said bottom surface.
6. The design structure according to claim 1 , said concentration of said first dopant in said diffusion region being less than approximately 1×10 17 cm −3 .
7. The design structure according to claim 1 ,
said third semiconductor layer comprising silicon and said second dopant,
said second semiconductor layer further comprising an implant region below said diffusion region, said implant region being adjacent to said third semiconductor layer and extending vertically from said third semiconductor layer towards said top surface of said second semiconductor layer, said implant region further being separated from said top surface of said second semiconductor layer by approximately 0.03 μm, said implant region being narrower in width than said diffusion region and comprising said second dopant at a higher concentration than in any other region of said second semiconductor layer, wherein a concentration profile of said second dopant in said second semiconductor layer is approximately uniform within said implant region and decreases through said diffusion region such that a concentration of said second dopant in said implant region is greater than approximately ten times a concentration of said second dopant at said top surface.
8. The design structure according to claim 7 , said first dopant comprising a p-type dopant comprising boron and said second dopant comprising an n-type dopant comprising one of phosphorous, antimony and arsenic.
9. A design structure for a bipolar transistor,
said design structure comprising at least layout parameters, test patterns and other testing information and manufacturing line routing information for said semiconductor structure,
said design structure being embodied in a machine readable storage medium accessible by a machine that processes said design structure to produce said bipolar transistor, and
said bipolar transistor comprising:
a base layer having a bottom surface and comprising silicon germanium and a first dopant having a first conductivity type; and
a collector layer below and immediately adjacent to said base layer, said collector layer comprising silicon; and
a sub-collector layer below and immediately adjacent to said collector layer,
none of said base layer, said collector layer and said sub-collector layer being carbon-doped,
said collector layer having a top surface adjacent to said bottom surface and comprising a diffusion region at said top surface,
said diffusion region comprising both said first dopant and a second dopant having a second conductivity type different from said first conductivity type, and
said top surface comprising approximately no defects such that a peak concentration of said first dopant in said base layer adjacent to said bottom surface is at least 100 times greater than a concentration of said first dopant in said diffusion region of said collector layer.
10. The design structure according to claim 9 , said design structure comprising a netlist which describes a circuit.
11. The design structure according to claim 9 , said design structure residing on a storage medium as a data format used for the exchange of layout data of integrated circuits.
12. The design structure according to claim 9 , said design structure comprising at least one of test data files, characterization data, verification data, and design specifications.
13. The design structure according to claim 9 , said concentration of said first dopant in said base layer increasing from approximately 1×10 17 cm −3 at said bottom surface to said peak concentration at approximately 0.03 μm above said bottom surface, said peak concentration of said first dopant in said base layer being greater than approximately 1×10 19 cm −3 .
14. The design structure according to claim 9 , said concentration of said first dopant in said diffusion region being less than approximately 1×10 17 cm −3 .
15. The design structure according to claim 9 ,
said sub-collector layer comprising silicon and said second dopant,
said collector layer further comprising an implant region below said diffusion region, said implant region being adjacent to said sub-collector layer and extending vertically from said sub-collector layer towards said top surface of said collector layer, said implant region further being separated from said top surface of said collector layer by approximately 0.03 μm, said implant region being narrower in width than said diffusion region and comprising said second dopant at a higher concentration than in any other region of said collector layer, wherein a concentration profile of said second dopant in said collector layer is approximately uniform within said implant region and decreases through said diffusion region such that a concentration of said second dopant at said implant region is greater than approximately ten times a concentration of said second dopant at said top surface.
16. The design structure according to claim 15 , said implant region further comprising a selective implant collector region.
17. The design structure according to claim 9 , having both a current-gain cut-off frequency (F t ) of greater than approximately 365.00 GHz and a maximum oscillation frequency (F max ) of greater than approximately 255.00 GHz.
18. The design structure according to claim 9 , having a collector-base capacitance (Ccb) less than approximately 3.40 fF and a sheet base resistance (Rbb) less than approximately 110.00 Ohms.