Semiconductor device and method of fabricating the same
View Patent ↗A semiconductor device and a fabricating method thereof are provided. The semiconductor device can include a first chip having transistors of only the NMOS type, a second chip having transistors of only the PMOS type, and an interconnection electrically connecting the first and second chips to each other. By forming NMOS and PMOS transistors on separate chips, the total number of implant photo processes can be decreased, thereby reducing the fabrication cost.
1. A semiconductor device, comprising:
a first chip comprising transistors that are only of the n-channel metal oxide semiconductor (NMOS) type;
a second chip comprising transistors that are only of the p-channel metal oxide semiconductor (PMOS) type;
an interconnection electrically connecting the first chip and the second chip; and
a third chip electrically connected to the first chip and the second chip, wherein the third chip comprises cell driving transistors for driving the transistors of the first chip and the transistors of the second chip.
2. A semiconductor device, comprising:
a first chip comprising transistors that are only of the n-channel metal oxide semiconductor (NMOS) type;
a second chip comprising transistors that are only of the p-channel metal oxide semiconductor (PMOS) type;
an interconnection electrically connecting the first chip and second chip;
a third chip comprising cell driving-NMOS transistors; and
a fourth chip comprising cell driving-PMOS transistors.
3. A method of fabricating a semiconductor device, comprising:
forming transistors on a first chip, wherein all transistors formed on the first chip are NMOS transistors;
forming transistors on a second chip, wherein all transistors formed on the second chip are PMOS transistors; and
electrically connecting the first chip and the second chip,
wherein the first chip and the second chip are arranged adjacent to each other in the same plane; and wherein the method further comprises:
preparing a third chip comprising cell driving transistors for driving the transistors of the first chip and the transistors of the second chip; and
electrically connecting the third chip to the first chip and the second chip to provide a system by interconnection structure.
4. The method according to claim 3 , wherein the first chip is formed on a first wafer, and wherein the second chip is formed on a second wafer.
5. The method according to claim 3 , wherein the semiconductor device is SRAM.
6. The method according to claim 3 , wherein four NMOS transistors in the first chip and two PMOS transistors in the second chip are electrically connected to form a SRAM cell.
7. The method according to claim 3 , wherein electrically connecting the third chip to the first chip and the second chip comprises forming interconnections.
8. The method according to claim 3 , wherein forming transistors on the first chip comprises forming p-wells in an NMOS active area of the first chip.
9. The method according to claim 3 , wherein forming transistors on the second chip comprises forming n-wells in a PMOS active area of the second chip.
10. A method of fabricating a semiconductor device, comprising:
forming transistors on a first chip, wherein all transistors formed on the first chip are NMOS transistors;
forming transistors on a second chip, wherein all transistors formed on the second chip are PMOS transistors; and
electrically connecting the first chip and the second chip,
wherein the first chip and the second chip are arranged adjacent to each other in the same plane; wherein the method further comprises:
preparing a third chip comprising cell driving-NMOS transistors; and
preparing a fourth chip comprising cell driving-PMOS transistors.
11. The method according to claim 10 , wherein the first chip is formed on a first wafer, and wherein the second chip is formed on a second wafer, and wherein the third chip is formed on a third wafer, and wherein the fourth chip is formed on a fourth wafer.
12. The method according to claim 10 , wherein the first chip and the third chip are formed on a first wafer, and wherein the second chip and the fourth chip are formed on a second wafer.
13. The method according to claim 10 , further comprising electrically connecting the third chip and the fourth chip to the first chip and the second chip to provide a system by interconnection structure.
14. The method according to claim 13 , wherein electrically connecting the third chip and the fourth chip to the first chip and the second chip comprises forming interconnections.