Trench-capacitor DRAM device and manufacture method thereof
View Patent ↗A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.
1. A dual-trench capacitor structure, comprising:
a semiconductor substrate having a main surface;
two independent trenches in close proximity to each other in the semiconductor substrate;
a ridge made of an insulating material and positioned between the two independent trenches, wherein the ridge's top surface is lower than the main surface of the semiconductor substrate;
an insulation liner conformally lining interior surface of the two independent trenches, and a part of the insulation liner extending to a ridge's top surface;
a bottom plate electrode covering the insulation liner and overlying the ridge within the two independent trenches;
a capacitor dielectric layer on the bottom plate electrode, and overlapping the ridge entirely; and
two storage nodes respectively filling the two independent trenches, wherein the storage nodes are isolated from each other.
2. The dual-trench capacitor structure according to claim 1 wherein the ridge is formed from a shallow trench isolation (STI) structure.
3. The dual-trench capacitor structure according to claim 1 wherein the storage node is substantially coplanar with the main surface of the semiconductor substrate.
4. The dual-trench capacitor structure according to claim 1 wherein the insulation liner comprises silicon oxide.
5. The dual-trench capacitor structure according to claim 4 wherein the insulation liner has a thickness of 30-300 angstroms.
6. The dual-trench capacitor structure according to claim 1 wherein the capacitor dielectric layer comprises oxide-nitride-oxide (ONO) dielectric.
7. The dual-trench capacitor structure according to claim 1 wherein a passing gate is positioned on and entirely overlaps the capacitor dielectric layer directly above the ridge.
8. The dual-trench capacitor structure according to claim 1 further comprising a control gate on the semiconductor substrate with a source/drain in the semiconductor substrate, and a local contact plug directly contacting the storage node and the source/drain for electrically connecting the storage node with the source/drain.
9. The dual-trench capacitor structure according to claim 1 , wherein the capacitor dielectric layer on the ridge is higher than the main surface of the semiconductor substrate.
10. A dual-trench capacitor structure, comprising:
a semiconductor substrate having a main surface;
two independent trenches in close proximity to each other in the semiconductor substrate;
a ridge between the two independent trenches;
an insulation liner conformally lining interior surface of the two independent trenches, and a part of the insulation liner extending to a ridge's top surface, wherein a top surface of the insulation liner positioned on the ridge's top surface is lower than the main surface of the semiconductor substrate;
a bottom plate electrode covering the insulation liner and overlying the ridge within the two independent trenches;
a capacitor dielectric layer on the bottom plate electrode, and overlapping the ridge entirely; and
two storage nodes respectively filling the two independent trenches, wherein the storage nodes are isolated from each other.