Low fabrication cost, fine pitch and high reliability solder bump
A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.
1 . A chip comprising:
a semiconductor substrate;
a dielectric layer over said semiconductor substrate;
a pad over said dielectric layer;
a passivation layer over said dielectric layer, an opening in said passivation layer exposing said pad, wherein said passivation layer comprises silicon nitride; and
a bump over said semiconductor substrate, wherein said bump is connected to said pad through said opening, and wherein said bump comprises a metal layer over said semiconductor substrate, wherein said metal layer is connected to said pad through said opening, a copper pillar over said metal layer, wherein said copper pillar has a height between 10 micrometers and 100 micrometers, and a nickel layer over said copper pillar, wherein said nickel layer has a thickness between 1 and 10 micrometers, wherein said copper pillar has a first transverse dimension smaller than a second transverse dimension of said nickel layer and smaller than a third transverse dimension of said metal layer, wherein said copper pillar has a first sidewall recessed from a second sidewall of said nickel layer and recessed from a third sidewall of said metal layer, wherein a distance between said first sidewall and said second sidewall is greater than 0.2 micrometers, wherein said metal layer has a top surface facing said copper pillar, wherein said top surface has a first region directly under said copper pillar and a second region not under said copper pillar, and wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar.
2 . The chip of claim 1 , wherein said semiconductor substrate comprises silicon.
3 . The chip of claim 1 , wherein said pad comprises aluminum.
4 . The chip of claim 1 , wherein said pad comprises copper.
5 . The chip of claim 1 , wherein said metal layer comprises titanium.
6 . The chip of claim 1 , wherein said metal layer comprises copper.
7 . The chip of claim 1 , wherein said metal layer has a thickness of between 500 and 2,000 angstroms.
8 . The chip of claim 1 , wherein said bump is further over said pad exposed by said opening.
9 . The chip of claim 1 , wherein said bump further comprises an electroplated metal on said nickel layer.
10 . The chip of claim 1 , wherein said bump further comprises a solder material on said nickel layer.
11 . A chip comprising:
a semiconductor substrate;
a dielectric layer over said semiconductor substrate;
a pad over said dielectric layer;
a passivation layer over said dielectric layer, an opening in said passivation layer exposing said pad, wherein said passivation layer comprises polymer; and
a bump over said semiconductor substrate, wherein said bump is connected to said pad through said opening, and wherein said bump comprises a metal layer over said semiconductor substrate, wherein said metal layer is connected to said pad through said opening, a copper pillar over said metal layer, wherein said copper pillar has a height between 10 micrometers and 100 micrometers, and a nickel layer over said copper pillar, wherein said nickel layer has a thickness between 1 and 10 micrometers, wherein said copper pillar has a first transverse dimension smaller than a second transverse dimension of said nickel layer and smaller than a third transverse dimension of said metal layer, wherein said copper pillar has a first sidewall recessed from a second sidewall of said nickel layer and recessed from a third sidewall of said metal layer, wherein a distance between said first sidewall and said second sidewall is greater than 0.2 micrometers, wherein said metal layer has a top surface facing said copper pillar, wherein said top surface has a first region directly under said copper pillar and a second region not under said copper pillar, and wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar.
12 . The chip of claim 11 , wherein said semiconductor substrate comprises silicon.
13 . The chip of claim 11 , wherein said pad comprises aluminum.
14 . The chip of claim 11 , wherein said pad comprises copper.
15 . The chip of claim 11 , wherein said metal layer comprises titanium.
16 . The chip of claim 11 , wherein said metal layer comprises copper.
17 . The chip of claim 11 , wherein said passivation layer comprises polyimide.
18 . The chip of claim 11 , wherein said bump is further over said pad exposed by said opening.
19 . The chip of claim 11 , wherein said bump further comprises an electroplated metal on said nickel layer.
20 . The chip of claim 11 , wherein said bump further comprises a solder material on said nickel layer.