Method to enhance device performance with selective stress relief
View Patent ↗A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.
1. A method for forming a semiconductor device comprising:
providing a substrate having first and second regions defined thereon, the first region comprising a first transistor and the second region comprising a second transistor;
forming a stress relief layer over the substrate covering the first and second regions and patterning the stress relief layer to remove the stress relief layer from the first region while leaving the stress relief layer on the second region over the second transistor; and
forming a stress layer on first and second regions of the substrate, the stress layer having a first stress, the stress layer covering the stress relief layer on the second region,
wherein the first stress of the stress layer improves the performance of the first transistor, and
the stress relief layer comprises a neutral stress or a second stress opposite the first stress of the stress layer to reduce performance degradation of the second transistor caused by the first stress layer.
2. The method of claim 1 wherein:
the first transistor comprises a n-type transistor;
the second transistor comprises a p-type transistor;
the first stress comprises a tensile stress; and
the second stress comprises compressive stress.
3. The method of claim 2 wherein:
the stress relief layer comprises silicon oxide, silicon oxynitride or silicon nitride; and
the stress layer comprises silicon nitride, silicon oxynitride or silicon carbide.
4. The method of claim 3 wherein forming the stress relief layer comprises forming a stress relief layer having a thickness between 100 and 300 angstroms.
5. The method of claim 2 wherein:
the stress relief layer comprises silicon oxide; and
the stress layer comprises silicon nitride.
6. The method of claim 5 wherein forming the stress relief layer comprises forming a stress relief layer having a thickness between 100 and 300 angstroms.
7. The method of claim 2 wherein the stress layer exerts the first stress in source and drain regions of the first transistor, which exerts the first stress in a channel region of the first transistor in a direction of a channel length of the first transistor.
8. The method of claim 7 wherein the first stress is between about +0.4 GPa and +2.5 GPa.
9. The method of claim 1 wherein the stress layer exerts the first stress in source and drain regions of the first transistor, which exerts the first stress in a channel region of the first transistor in a direction of a channel length of the first transistor.
10. A method for forming a semiconductor device comprising:
defining first and second regions on a substrate;
forming first and second transistors in first and second regions;
forming a stress relief layer over the substrate covering the first and second regions and patterning the stress relief layer to remove the stress relief layer from the first region while leaving the stress relief layer on the second region over the second transistor; and
depositing a stress layer on first and second regions of the substrate, the stress layer having a first stress, the stress layer covering the stress relief layer on the second region,
wherein the first stress of the stress layer improves the performance of the first transistor, and
the stress relief layer comprises a neutral stress or a second stress opposite the first stress of the stress layer to reduce performance degradation of the second transistor caused by the first stress layer.
11. The method of claim 10 wherein the stress layer exerts the first stress in source and drain regions of the first transistor, which exerts the first stress in a channel region of the first transistor in a direction of a channel length of the first transistor.
12. The method of claim 10 wherein:
the first transistor comprises a n-type transistor;
the second transistor comprises a p-type transistor;
the first stress comprises a tensile stress; and
the second stress comprises compressive stress.
13. The method of claim 12 wherein:
the stress relief layer comprises silicon oxide, silicon oxynitride or silicon nitride; and
the stress layer comprises silicon nitride, silicon oxynitride or silicon carbide.
14. The method of claim 10 wherein:
the first transistor comprises a n-type transistor;
the second transistor comprises a p-type transistor;
the first stress comprises a tensile stress; and
the second stress comprises compressive stress.
15. The method of claim 10 wherein:
the stress relief layer comprises silicon oxide, silicon oxynitride or silicon nitride; and
the stress layer comprises silicon nitride, silicon oxynitride or silicon carbide.
16. A method for forming a semiconductor device comprising:
providing a substrate having first and second regions defined thereon, the first region comprising a first transistor and the second region comprising a second transistor;
forming a stress relief layer on the second region of the substrate to cover the second transistor by forming a stress relief layer over the substrate covering the first and second regions and patterning the stress relief layer to remove the stress relief layer from the first region while leaving the stress relief layer on the second region over the second transistor; and
forming a stress layer on first and second regions of the substrate, the stress layer having a first stress, the stress layer covering the stress relief layer on the second region.
17. The method of claim 16 wherein:
the first stress of the stress layer improves the performance of the first transistor; and
the stress relief layer comprises a neutral stress or a second stress opposite the first stress of the stress layer to reduce performance degradation of the second transistor caused by the first stress layer.
18. The method of claim 16 wherein the stress layer exerts the first stress in source and drain regions of the first transistor, which exerts the first stress in a channel region of the first transistor in a direction of a channel length of the first transistor.