Granted Patent B1

US 7,545,660 · App. 11/931,868 · Granted Jun 9, 2009

Abstract

Claims (11)

1. An apparatus comprising:

a plurality of memory cells arranged in a row;

two or more match lines running substantially parallel to said row; and

means for connecting one or more of said plurality of memory cells arranged in said row to said two or more match lines.

2. An apparatus comprising:

a plurality of memory cells arranged in a row;

two or more match lines running substantially parallel to said row; and

means for connecting two or more subsets of said plurality of memory cells arranged in said row to said two or more match lines.

3. An apparatus comprising:

means for connecting memory cells in a row to two or more match lines; and

means for connecting said two or more match lines to one or more circuits.

Assignments (10)