Memory device employing three-level cells and related methods of managing
View Patent ↗A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.
1. A memory device comprising:
an array of addressable three-level memory cells;
a coding circuit to be input with three-bit strings and to generate corresponding ternary strings based upon a code;
a program circuit to be input with the ternary strings and to store them in respective pairs of three-level memory cells;
a read circuit to read stored ternary strings in the respective pairs of three-level memory cells; and
a decoding circuit to be input with the stored ternary strings and to generate corresponding strings of three bits based upon the code.
2. The memory device of claim 1 wherein said array is organized in words for storing a string of sixteen bits; and wherein each word comprises a first three-level cell to store a bit of the string of sixteen bits, and five pairs of three-level memory cells to store the remaining fifteen bits.
3. The memory device of claim 2 wherein the bit stored in the first three-level cell is a most significant bit.
4. The memory device of claim 2 wherein the bit stored in the first three-level cell is a least significant bit.
5. The memory device of claim 2 further comprising an array of eleven sense amplifiers for each three-level cell of the word to be read and to generate a respective pair of bits representing a program level of a read cell; and wherein for each word to be read, said decoding circuit comprises:
an array of five decoding logic circuits, each input with two pairs of representative bits to be generated by a respective sense amplifier of one of the pairs of three-level memory cells, and to generate a corresponding triplet of bits; and
a logic decoding circuit to be input with the representative pair of bits generated by a sense amplifier associated to the first three-level cell, the first three-level cell storing a single bit and to output a read bit.
6. The memory device of claim 1 wherein said array is organized based upon a FLASH NOR architecture.
7. A method of managing a memory including addressable three-level memory cells, the method comprising:
storing strings of three bits by at least
coding the strings in corresponding ternary strings based upon a code, and
storing each of the ternary strings in a respective pair of three-level memory cells by supplying program pulses to the pair of three-level memory cells; and
reading the stored strings from the memory by at least
reading respective stored ternary strings from respective pairs of three-level memory cells, and
decoding each ternary string into a corresponding string of three bits based upon the code.
8. The method of claim 7 wherein the three-level memory cells of the memory are organized in words, each word comprising eleven three-level memory cells, and for storing a string of sixteen bits; and further comprising:
storing a bit of the string of sixteen bits in a first three-level cell, the remaining bits organized in triplets; and
storing the remaining five triplets of bits of the string of sixteen bits in respective five pairs of three-level memory cells of the word.
9. The method of claim 8 wherein the first three-level cell storing the bit is erased for storing a high logic level; and wherein the first three-level cell is programmed in one of the other two levels for storing a low logic level.
10. The method of claim 9 wherein the bit stored in the first three-level cell is the most significant bit.
11. The method of claim 9 wherein the bit stored in the first three-level cell is the least significant bit.
12. The method of claim 7 wherein the strings of three bits are coded in pairs of three-level memory cells based upon the following code:
111
AA
110
AB
101
BB
011
BA
010
AC or CA
100
CB
001
BC
000
CC.
13. The method of claim 12 wherein the pairs of three-level memory cells store strings of three adjacent bits of a same word.
14. The method of claim 12 further comprising programming a pair of adjacent bits belonging to at least one of a same initial string and two initial adjacent strings by identifying pairs of three-level memory cells to be programmed for encoding the strings of three bits and programming each pair of memory cells by at least:
determining if a least significant or a most significant cell of the pair of three-level memory cells is programmed in a state corresponding to an intermediate program level and programming the state corresponding to the intermediate program level; and
determining if the least significant or the most significant cell of the pair of three-level memory cells is programmed in a state corresponding to a high program level and programming the state corresponding to the high program level.
15. The method of claim 7 wherein the strings of three bits are coded in pairs of three-level memory cells based upon the following code:
111
AA
110
BA
101
BB
011
AB
010
AC or CA
100
BC
001
CB
000
CC.
16. The method of claim 15 wherein the pairs of three-level memory cells store strings of three adjacent bits of a same word.
17. A memory device comprising:
an array of addressable memory cells with k levels, k being different from a power of two;
a coding circuit to be input with strings of N bits for storing and to generate corresponding k-level strings based upon a code;
a program circuit to be input with the k-level strings and to store the k-level strings in respective groups of c memory cells with k levels;
a read circuit to read data stored in groups of c memory cells with k levels and to generate corresponding stored k-level strings; and
a decoding circuit to be input with the stored k-level strings and to generate corresponding strings of N bits read from the memory based upon the code.
18. The memory device of claim 17 wherein said array is organized in pages of a set number of words, each word for storing a string of sixteen bits; wherein k comprises six; wherein N comprises five; wherein c comprises two; and wherein k-level strings comprises senary strings, said coding circuit to store the senary strings in respective pairs of six-level memory cells.
19. A method of managing a memory device that includes an array of addressable memory cells with k levels, k being different from a power of two, the method comprising:
storing strings of N bits by at least
coding the strings of N bits in corresponding k-level strings based upon a code, and
storing each of the k-level strings in respective groups of c memory cells with k levels by providing program pulses to the groups of c memory cells with k levels; and
reading strings of N bits from the memory by at least
reading respective k-level strings stored in respective groups of c memory cells with k levels, and
decoding each read k-level string into a corresponding string of N bits based upon the code.
20. The method of claim 19 wherein k comprises six; wherein N comprises five; wherein c comprises two; and wherein k-level strings comprises senary strings, said coding circuit storing the senary strings in respective pairs of six-level memory cells.