Nonvolatile semiconductor memory device and nonvolatile memory system

1. A nonvolatile semiconductor memory device comprising;

a memory cell array including a plurality of electrically rewritable nonvolatile memory cells arranged in series, at least one of said memory cells storing data using a plurality of threshold levels;

a threshold level storage section storing a programming method switch threshold level on which a first programming method and a second programming method are switched;

a comparison circuit comparing said programming method switch threshold level with a programming data threshold level and outputting a comparison result;

a control signal generation circuit setting said first programming method or said second programming method based on said comparison result and outputting a control signal corresponding to said first programming method or said second programming method; and

a voltage generation circuit generating a programming voltage and an intermediate voltage which are applied to said at least one memory cell based on said control signal.

2. The nonvolatile semiconductor memory device according to claim 1 ,

wherein said voltage generation circuit generates said intermediate voltage according to said programming data threshold level.

3. The nonvolatile semiconductor memory device according to claim 1 ,

wherein said memory cell array includes a plurality of word lines being connected to control gates of said memory cells and a plurality of bit lines being connected to a drain side end of said serially-connected memory cells, and

wherein said programming voltage is applied to at least one of said word lines and said intermediate voltage is applied to at least one of said bit lines according to said first programming method or said second programming method.

4. The nonvolatile semiconductor memory device according to claim 1 ,

wherein said control signal generation circuit sets said first programming method in case said programming data threshold level is no less than said programming method switch threshold level and sets said second programming method in case said programming data threshold level is less than said programming method switch threshold level.

5. The nonvolatile semiconductor memory device according to claim 3 ,

wherein in said first programming method, said programming voltage is applied to said at least one word line with a first voltage applied to said at least one bit line to execute a write operation or with a second voltage applied to said at least one bit line to execute a write-inhibit operation, and a verify voltage corresponding to said programming data threshold level is applied to said at least one word line to execute a verify operation, said second voltage is higher than said first voltage, and

wherein in said second programming method, said programming voltage is applied to said at least one word line with said first voltage applied to said at least one bit line to execute said write operation, and a low verify voltage lower than said verify voltage corresponding to said programming data threshold level is applied to said at least one word line to execute a low verify operation, and after passing said low verify operation, said programming voltage is applied to said at least one word line with said intermediate voltage applied to said at least one bit line to execute said write operation, and said verify voltage corresponding to said programming data threshold level is applied to said at least one word line to execute said verify operation, said intermediate voltage is higher than said first voltage and lower than said second voltage.

6. The nonvolatile semiconductor memory device according to claim 5 ,

wherein said memory cell array includes a first select gate line connected to a plurality of first select gate transistors adjacent to a source side end of said serially-connected memory cells and a second select gate line connected to a plurality of second select gate transistors adjacent to said drain side end of serially-connected memory cells, and

wherein said memory cells connected to the word line adjacent to said first select gate line are programmed with switching said first programming method and said second programming method, and said memory cells connected to the word lines not adjacent to said first select gate line are programmed with said second programming method.

7. The nonvolatile semiconductor memory device according to claim 5 ,

wherein said memory cell array includes a first select gate line connected to a plurality of first select gate transistors adjacent to a source side end of said serially-connected memory cells and a second select gate line connected to a plurality of second select gate transistors adjacent to said drain side end of serially-connected memory cells, and

wherein said memory cells connected to the word line adjacent to said first select gate line or said second select gate line are programmed with switching said first programming method and said second programming method, and said memory cells connected to the word lines not adjacent to said first select gate line and said second select gate line are programmed with said second programming method.

8. The nonvolatile semiconductor memory device according to claim 3 ,

wherein in said first programming method, said programming voltage is applied to said at least one word line with a first voltage applied to said at least one bit line to execute a write operation or with a second voltage applied to said at least one bit line to execute a write-inhibit operation, and a verify voltage corresponding to said programming data threshold level is applied to said word line to execute a verify operation, said second voltage is higher than said first voltage, and

wherein in said second programming method, said programming voltage is applied to said at least one word line with said first voltage applied to said at least one bit line to execute said write operation, and a low verify voltage lower than said verify voltage corresponding to said programming data threshold level is applied to said at least one word line to execute a low verify operation, and after passing said low verify operation, said programming voltage is applied to said at least one word line with said intermediate voltage applied to said at least one bit line to execute said write operation, and said verify voltage corresponding to said programming data threshold level is applied to said at least one word line to execute said verify operation, said intermediate voltage is increased or decreased corresponding to said programming data threshold level within range of between said first voltage and said second voltage.

9. The nonvolatile semiconductor memory device according to claim 8 ,

wherein said memory cell array includes a first select gate line connected to a plurality of first select gate transistors adjacent to a source side end of said serially-connected memory cells and a second select gate line connected to a plurality of second select gate transistors adjacent to said drain side end of serially-connected memory cells, and

wherein said memory cells connected to the word line adjacent to said first select gate line are programmed with switching said first programming method and said second programming method, and said memory cells connected to the word lines not adjacent to said first select gate line are programmed with said second programming method.

10. The nonvolatile semiconductor memory device according to claim 8 ,

wherein said memory cell array includes a first select gate line connected to a plurality of first select gate transistors adjacent to a source side end of said serially-connected memory cells and a second select gate line connected to a plurality of second select gate transistors adjacent to said drain side end of serially-connected memory cells, and

wherein said memory cells connected to the word line adjacent to said first select gate line or said second select gate line are programmed with switching said first programming method and said second programming method, and said memory cells connected to the word lines not adjacent to said first select gate line and said second select gate line are programmed with said second programming method.

11. The nonvolatile semiconductor memory device according to claim 3 ,

wherein in said first programming method, said programming voltage is applied to said at least one word line with a first voltage applied to said at least one bit line to execute a write operation or with a second voltage applied to said at least one bit line to execute a write-inhibit operation, and a verify voltage corresponding to said programming data threshold level is applied to said at least one word line to execute a verify operation, said second voltage is higher than said first voltage, and

wherein in said second programming method, said programming voltage is applied to said at least one word line and said first voltage is applied to said at least one bit line to execute said write operation, and a low verify voltage lower than said verify voltage corresponding to said programming data threshold level is applied to said at least one word line to execute a low verify operation, and after passing said low verify operation, said programming voltage is once stepped up and applied to said at least one word line with said first voltage applied to said at least one bit line to execute said write operation.

12. The nonvolatile semiconductor memory device according to claim 11 ,

wherein said memory cell array includes a first select gate line connected to a plurality of first select gate transistors adjacent to a source side end of said serially-connected memory cells and a second select gate line connected to a plurality of second select gate transistors adjacent to said drain side end of serially-connected memory cells, and

wherein said memory cells connected to the word line adjacent to said first select gate line are programmed with switching said first programming method and said second programming method, and said memory cells connected to the word lines not adjacent to said first select gate line are programmed with said second programming method.

13. The nonvolatile semiconductor memory device according to claim 11 ,

wherein said memory cell array includes a first select gate line connected to a plurality of first select gate transistors adjacent to a source side end of said serially-connected memory cells and a second select gate line connected to a plurality of second select gate transistors adjacent to said drain side end of serially-connected memory cells, and

wherein said memory cells connected to the word line adjacent to said first select gate line or said second select gate line are programmed with switching said first programming method and said second programming method, and said memory cells connected to the word lines not adjacent to said first select gate line and said second select gate line are programmed with said second programming method.

14. A nonvolatile semiconductor memory device comprising:

a memory cell array including a plurality of electrically rewritable nonvolatile memory cells arranged in series, at least one of said memory cells storing data using a plurality of threshold levels;

a number of times storage section storing a programming method switch number of step-up-times on which a first programming method and a second programming method are switched;

a counter circuit counting a number of step-up-times when a programming voltage applied to said at least one memory cell is stepped up and outputting said number of step-up-times;

a comparison circuit comparing said number of step-up-times with said programming method switch number of step-up-times and outputting a comparison result;

a control signal generation circuit sets said first programming method or said second programming method based on a comparison result and outputting a control signal corresponding to said first programming method or said second programming method; and

a voltage generation circuit generating said programming voltage and an intermediate voltage which are applied to said at least one memory cell based on said control signal.

15. The nonvolatile semiconductor memory device according to claim 14 ,

wherein said control signal generation circuit sets said first programming method in case said number of step-up-times is no less than said programming method switch number of step-up-times, and sets said second programming method in case said number of step-up-times is less than said programming method switch number of step-up-times.

16. The nonvolatile semiconductor memory device according to claim 14 ,

wherein said control signal generation circuit includes said counter circuit.

17. The nonvolatile semiconductor memory device according to claim 14 ,

wherein said comparison circuit includes a register storing said comparison result.

18. A nonvolatile memory system comprising:

a memory cell array including a plurality of electrically rewritable nonvolatile memory cells arranged in series, at least one said memory cells storing data using a plurality of threshold levels;

a threshold level storage section storing a programming method switch threshold level on which a first programming method and a second programming method are switched;

a comparison circuit comparing said programming method switch threshold level with a programming data threshold level and outputting a comparison result;

a control signal generation circuit setting said first programming method or said second programming method based on said comparison result and outputting a control signal corresponding to said first programming method or said second programming method;

a voltage generation circuit generating a programming voltage and an intermediate voltage which are applied to said at least one memory cell based on said control signal; and

an external controller changing said programming method switch threshold level stored in said threshold level storage section according to a command inputted from an system apparatus.

19. The nonvolatile memory system according to claim 18 ,

wherein said memory cell array includes a plurality of word lines being connected to control gates of said memory cells and a plurality of bit lines being connected to a drain side end of said serially-connected memory cells, and

wherein said programming voltage is applied to at least one word line and said intermediate voltage is applied to at least one bit line according to said first programming method or said second programming method.

20. The nonvolatile memory system according to claim 19 ,

wherein said control signal generation circuit sets said first programming method in case said programming data threshold level is no less than said programming method switch threshold level and sets said second programming method in case said programming data threshold level is less than said programming method switch threshold level.