Semiconductor device package of stacked semiconductor chips with spacers provided therein
View Patent ↗A semiconductor device package includes a plurality of stacked semiconductor chips and a spacer interposed therebetween. The spacer includes a first spacer and a second spacer stacked on one another. The first and the second spacers have different principal surfaces. If the second spacer has a larger principal surface than the first spacer, flexure of the upper semiconductor chip can be avoided.
1. A semiconductor device package comprising:
a first semiconductor chip;
a first spacer placed above the first semiconductor chip;
a second spacer placed above the first spacer;
a second semiconductor chip placed above the second spacer;
a first bonding layer interposed between the first semiconductor chip and the first spacer and bonding the first spacer to the first semiconductor chip; and
a second bonding layer interposed between the second spacer and the second semiconductor chip and bonding the second semiconductor chip to the second spacer,
wherein the second spacer has a larger principal surface than that of the first spacer.
2. The semiconductor device package of claim 1 , wherein a total thickness of the first spacer and the second spacer is a thickness required for wire bonding of a semiconductor chip located below the spacer.
3. The semiconductor device package of claim 1 , wherein either one of the first spacer and second spacer is thinner than a semiconductor chip.
4. The semiconductor device package of claim 1 , wherein the first spacer and the second spacer have substantially the same thickness.
5. The semiconductor device package of claim 1 , wherein the second spacer has a larger principal surface than the second semiconductor chip.
6. The semiconductor device package of claim 5 , wherein an electromagnetic wave shielding film is formed on at least all over one surface of the second spacer.
7. The semiconductor device package of claim 6 , wherein the electromagnetic wave shielding film is an aluminum film.
8. The semiconductor device package according to claim 7 ,
wherein the first spacer and the second spacer are each formed of a silicon wafer.
9. The semiconductor device package according to claim 1 , further comprising:
a third semiconductor chip placed above the second semiconductor chip so as to expose an electrode of the second semiconductor chip.
10. A semiconductor device, comprising:
a first semiconductor chip placed on a substrate;
a first bonding layer placed on the first semiconductor chip;
a first spacer placed on the first bonding layer, the first spacer having a smaller principal surface than that of the first semiconductor chip;
a second spacer placed above the first spacer, the second spacer having a larger principal surface than that of the first spacer;
a second bonding layer placed on the second spacer; and
a second semiconductor chip placed on the second bonding layer.
11. A semiconductor device according to claim 10 ,
wherein a principal surface of the second spacer is larger than that of the second semiconductor chip.
12. A semiconductor device according to claim 11 ,
wherein the second spacer has a metal film over the principal surface of the second spacer.