Field insulator FET device and fabrication method thereof
View Patent ↗A FinFET and a fabrication method thereof. The FinFET device includes an SOI substrate realized through a substrate, a buried oxide layer formed on the substrate, and a silicon epitaxial layer formed on predetermined areas of the buried oxide layer. A gate oxide layer is formed on the silicon epitaxial layer, and a gate electrode is formed on the gate oxide layer. A field insulator is formed on exposed areas of the buried oxide layer to thereby separate adjacent silicon epitaxial layers. Side surfaces of the silicon epitaxial layer are flattened through heat treatment. The fabrication method for a FinFET device includes forming the gate oxidation layer and the gate electrode on the SOI substrate; forming the mask pattern on the gate electrode; forming the trench by etching using the mask pattern as a mask; performing heat treatment to flatten the side surfaces of the silicon epitaxial layer; and forming the field insulator in the trench.
1. A field insulator field effect transistor device, comprising:
a silicon on insulator substrate that includes a substrate, a buried oxide layer formed on the substrate, and a silicon epitaxial layer patterned to be formed on portions of the buried oxide layer;
a gate oxide layer formed on the silicon epitaxial layer;
a gate electrode formed on the gate oxide layer; and
a field insulator formed on the exposed buried oxide layer to separate adjacent silicon epitaxial layers,
wherein side surfaces of the silicon epitaxial layer are flattened through a heat treatment perfomed at a temperature of about 850° C. to about 1150° C. and in one a hydrogen gas atmosphere and a heavy hydrogen gas atmosphere without forming an oxide on the side surfaces.
2. The field insulator field effect transistor device of claim 1 , wherein striation and facet regions of the side surfaces of the silicon epitaxial layer are flattened by the heat treatment.
3. The field insulator field effect transistor device of claim 1 , wherein the heat treatment is performed in a deuterium D 2 gas atmosphere.
4. The field insulator field effect transistor device of claim 1 , wherein the heat treatment is performed at a temperature in a range of about 1050° C. to about 1150° C.
5. The field insulator field effect transistor device of claim 1 , wherein striation and facet regions of the side surfaces of the silicon epitaxial layer are flattened by the heat treatment.
6. The field insulator field effect transistor device of claim 1 , wherein an upper surface of the field insulator is higher than an upper surface of the gate electrode.
7. The field insulator field effect transistor device of claim 1 , wherein an upper surface of the field insulator is flattened through chemical-mechanical polishing.
8. The field insulator field effect transistor device of claim 1 , wherein the gate electrode is a polycrystalline silicon layer.