Semiconductor device and audio processor chip
View Patent ↗An audio processor chip includes a DSP for decoding audio data, a first DAC for performing a D/A conversion to the digital data obtained from the DSP, a PLL circuit for generating a clock signal for the first DAC to supply it to the first DAC and a clock output external terminal for outputting the clock signal obtained from the PLL circuit to a second DAC of an AFE. The first DAC 142 outputs an analog signal obtained from the D/A conversion to an analog mixer and the analog mixer performs a mixing process to the analog signal to output.
1. A semiconductor device comprising:
a first D/A converter circuit formed on a first semiconductor chip couples to a common node;
a second D/A converter circuit formed on a second semiconductor chip couples to the common node;
a clock generation circuit formed on the first semiconductor chip, couples to the common node, to generate a clock signal for the first D/A converter circuit and supply it to the first D/A converter circuit and a clock signal for the second D/A converter circuit and supply it to the second D/A converter circuit;
a main processor formed on a third semiconductor chip that connects with the first D/A converter circuit, wherein the first D/A converter circuit receives a first data from the main processor; and
a digital signaling processor formed on the first semiconductor chip that couples between the main processor and the second D/A converter circuit, wherein the second D/A converter circuit receives a third data generated by the digital signaling processor based on a second data supplied from the main processor.
2. The semiconductor device according to claim 1 , wherein the main processor supplies the first data to the first D/A converter circuit in the first mode, and supplies the second data to the second D/A converter circuit through the digital signaling processor in the second mode.
3. The semiconductor device according to claim 2 , further comprising;
a control circuit renders the second D/A converter circuit inactive in the first mode, and renders the second D/A converter circuit active in the second mode.
4. A semiconductor device comprising:
a first D/A converter circuit couples to a common node;
a second D/A converter circuit couples to the common node;
a clock generation circuit, couples to the common node, to generate a clock signal for the first D/A converter circuit and supply it to the first D/A converter circuit and a clock signal for the second D/A converter circuit and supply it to the second D/A converter circuit;
a main processor connects with the first D/A converter circuit, wherein the first D/A converter circuit receives a first data from the main processor; and
a digital signaling processor couples between the main processor and the second D/A converter circuit, wherein the second D/A converter circuit receives a third data generated by the digital signaling processor based on a second data supplied from the main processor.