Transistor and method for manufacturing same
View Patent ↗An improved coupling stability between the source region and the source electrode of the transistor is achieved. In the method for manufacturing the MOSFET, the p-type base region is formed in a semiconductor layer, and after the p-type base region is formed in the surface portion of the n+ type source region, the higher concentration source region extending from the side edge of the n+ type source region to the lateral side of the n+ type source region is formed in the surface portion of the p-type base region. Then, the source electrode coupled to the higher concentration source region is formed. This allows providing an improved coupling stability between the source electrode and the source region when a misalignment is occurred in the location for forming the source electrode during the formation of the source electrode to be coupled to the first source region.
1. A method for manufacturing a transistor, comprising:
forming, in a semiconductor layer having a first conductivity type, a base region having a second conductivity type;
forming a first source region having the first conductivity type in said base region;
forming a second source region having the first conductivity type in said base region, wherein said second source region is in contact with said first source region and an impurity concentration of said second source region is different from an impurity concentration of said first source region; and
forming a source electrode coupled to both said second source region and said base region.
2. The method for manufacturing a transistor as set forth in claim 1 , wherein said forming the second source region includes forming said second source region so as to be overlapped with a portion of said first source region by injecting an impurity by an oblique-rotating injection.
3. The method for manufacturing a transistor as set forth in claim 1 , further comprising:
selectively removing a predetermined location of said semiconductor layer to form a trenched portion;
forming a gate insulating film and a gate electrode in said trenched portion; and
forming an interlayer insulating film to cover an upper portion of said gate electrode.
4. The method for manufacturing a transistor as set forth in claim 3 , wherein said base region is a first base region and the method further comprises forming a second base region in the surface portion of said first base region, at a location remote from said first source region, wherein said second base region contains the impurity of the second conductivity type at higher concentration than both in said first base region and in said second source region.
5. The method for manufacturing a transistor as set forth in claim 3 , wherein said forming said base region includes injecting an impurity of the second conductivity type into said layer having the first conductivity type with said trenched portion formed therein to form said base region, wherein said forming the first source region includes injecting an impurity of the first conductivity type into the lateral side of said gate electrode in said base region to form said first source region that is in contact with a side surface of said trenched portion, and wherein said forming the second source region by injecting an impurity having the first conductivity type uses said interlayer insulating film as a mask.
6. The method for manufacturing a transistor as set forth in claim 1 , wherein the impurity concentration of said second source region is greater than the impurity concentration of said first source region.
7. The method for manufacturing a transistor as set forth in claim 6 , wherein said forming the second source region includes forming said second source region so as to be overlapped with a portion of said first source region by injecting an impurity by an oblique-rotating injection.
8. A transistor device, comprising:
a semiconductor layer having a first conductivity type;
a base region having a second conductivity type provided in a surface portion of said semiconductor layer, wherein the second conductivity type is inverse to the first conductivity type;
a gate electrode formed in a trenched portion that is provided in said base region;
a first source region having the first conductivity type provided in the lateral side of said gate electrode and provided in a surface portion of said base region;
a second source region having the first conductivity type provided in the surface portion of said base region and in contact with said first source region, an impurity concentration of said second source region is different from an impurity concentration of said first source region; and
a source electrode coupled to said second source region and said base region.
9. The device as set forth in claim 8 , wherein the impurity concentration of said second source region is greater than the impurity concentration of said first source region.
10. The device as set forth in claim 9 , wherein said second source region is overlapped with a portion of said first source region.
11. The device as set forth in claim 8 , wherein said second source region is overlapped with a portion of said first source region.
12. A method for manufacturing a transistor, comprising:
forming, in a semiconductor layer having a first conductivity type, a base region having a second conductivity type;
forming a first source region having the first conductivity type in said base region;
forming a second source region having the first conductivity type in said base region, wherein said second source region is in contact with said first source region; and
forming a source electrode coupled to both said second source region and said base region,
wherein said forming the second source region includes forming said second source region so as to be overlapped with a portion of said first source region by injecting an impurity by an oblique-rotating injection.
13. The method for manufacturing a transistor as set forth in claim 12 , wherein an impurity concentration of said second source region is different from an impurity concentration of said first source region.
14. The method for manufacturing a transistor as set forth in claim 13 , wherein the impurity concentration of said second source region is greater than the impurity concentration of said first source region.