IP Library Granted Patent US 7,507,659
Granted Patent B2
US 7,507,659 · App. 11/939,064 · Granted Mar 24, 2009

Fabrication process of a semiconductor device

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Quick Facts
Patent No.
US 7,507,659
App. No.
11/939,064
Granted
Mar 24, 2009
Kind
B2
Abstract

A method for fabricating a semiconductor device has forming an opening defined by an inner wall surface in an insulation film, covering said inner wall surface with a Cu—Mn alloy layer, depositing a first Cu layer over said Cu—Mn alloy layer without exposing said Cu—Mn alloy layer to the air, depositing a second Cu layer over said first Cu layer and filling said opening with said second Cu layer, and forming a barrier layer over said inner wall surface as a result of a reaction between Mn in said Cu—Mn alloy layer and said insulation film.

Claims (27)

1. A method for fabricating a semiconductor device, comprising:

forming an opening defined by an inner wall surface in an insulation film;

covering said inner wall surface with a Cu—Mn alloy layer;

depositing a first Cu layer over said Cu—Mn alloy layer without exposing said Cu—Mn alloy layer to the air;

depositing a second Cu layer over said first Cu layer and filling said opening with said second Cu layer; and

forming a barrier layer over said inner wall surface as a result of a reaction between Mn in said Cu—Mn alloy layer and said insulation film.

2. The method as claimed in claim 1 , further comprising, after forming said Cu—Mn alloy layer but before depositing said first Cu layer, re-sputtering a surface of said Cu—Mn alloy layer.

3. The method as claimed in claim 1 , wherein said vacuum environment has a pressure of 10 −7 Pa or less.

4. The method as claimed in claim 1 , wherein said Cu—Mn alloy layer is formed by a sputtering process, said first Cu layer is formed by a sputtering process, and said second Cu layer is formed by an electrolytic plating process.

5. The method as claimed in claim 1 , wherein said first Cu layer is formed with a thickness of 3-10 nm.

6. A method for fabricating a semiconductor device, comprising:

forming an opening defined by an inner wall surface in an insulation film;

covering said inner wall surface with a Cu—Mn alloy layer;

terminating a surface of said Cu—Mn alloy layer with hydrogen;

depositing a Cu layer over said Cu—Mn alloy layer and filling g said opening with said Cu layer; and

forming a barrier layer over said inner wall surface as a result of a reaction between Mn in said Cu—Mn alloy layer and said insulation film.

7. The method as claimed in claim 6 , wherein hydrogen termination is conducted by carrying out a hydrogen plasma processing.

8. The method as claimed in claim 7 , wherein said hydrogen plasma processing is conducted at a temperature of 100-150° C.

9. A method for fabricating a semiconductor device, comprising:

forming an opening defined by an inner wall surface in an insulation film;

covering said inner wall surface with a Cu—Mn alloy layer;

depositing a Cu layer over said Cu—Mn alloy layer; and

forming a barrier layer over said inner wall surface as a result of a reaction between Mn in said Cu—Mn alloy layer and said insulation film,

wherein said method further comprises, after forming said Cu—Mn alloy layer before depositing said Cu layer, exposing a surface of said Cu—Mn alloy layer to a gas that forms a gaseous reaction product when reacted with a Mn oxide, or re-sputtering a surface of said Cu—Mn alloy layer.

10. The method as claimed in claim 9 , wherein exposing to said gas that forms said gaseous reaction product upon said Mn oxide is conducted at a temperature of 100-400° C.

11. The method as claimed in claim 9 , wherein forming said barrier layer is conducted while exposing to an ambient that forms a gaseous reaction product upon reaction with Mn.

12. The method as claimed in claim 10 , wherein said gas forming said gaseous reaction product upon reaction with Mn or Mn oxide is a gas containing at least one of formic acid, carboxylic acid, hexafluoroacetylacetonate, H 2 O and CO 2 .

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2007
From: OHTSUKA, NOBUYUKI; SHIMIZU, NORIYOSHI; NAKAO, YOSHIYUKI
To: FUJITSU LIMITED
Reel/Frame 020107/0704 →