Structure and fabrication method of flash memory
View Patent ↗A method for forming a flash memory cell and the structure thereof is disclosed. The flash memory cell includes a substrate, a first raised source/drain region and a second raised source/drain region separated by a trench in-between, a first charge-trapping spacer and a second charge-trapping spacer respectively on the sidewall of the first and second raised source/drain region, a gate structure covering the first and second spacers, the trench and the first and second raised source/drain regions and a gate oxide layer located between the gate structure and the first and second raised source/drain regions and the substrate. By forming the charge-trapping spacers with less e-distribution, the flash memory affords better erasure efficiency.
1. A structure of a flash memory, comprising:
a substrate;
a plurality of raised source/drain regions on the substrate;
a plurality of charge-trapping spacers on sidewalls of the raised source/drain regions;
a plurality of gate structures covering the charge-trapping spacers and the raised source/drain regions; and
an oxide layer located between the gate structure and the raised source/drain regions and between the gate structure and the substrate, wherein the gate structures are strip structures in parallel that function as word lines and run across above the raised source/drain regions that function as bit lines.
2. The structure of claim 1 , wherein each of the charge-trapping spacers consists of a composite oxide/nitride/oxide (ONO) structure.
3. The structure of claim 2 , wherein the composite oxide/nitride/oxide (ONO) structure comprises a tunnel oxide layer of about 40-60 angstroms, a silicon nitride layer of about 40-60 angstroms and a top oxide layer of about 40-60 angstroms.
4. The structure of claim 1 , wherein portions of the raised source/drain regions are overlapped with the gate structures and the charge-trapping spacers are disposed beneath the gate structures and right on the sidewalls of the overlapped portions of the raised source/drain regions.
5. The structure of claim 4 , wherein the word lines are perpendicular to the bit lines.
6. The structure of claim 1 , wherein the raised source/drain regions are strip structures arranged in parallel and with trenches in-between, and portions of the word lines are disposed within the trenches between the raised source/drain regions and covering the dielectric spacers.
7. The structure of claim 6 , wherein the word lines are perpendicular to the bit lines.
8. The structure of claim 6 , wherein a height of the raised source/drain regions is about 500-1000 angstroms and a depth of the trenches is about the same as the height of the raised source/drain regions.
9. A flash memory cell, comprising:
a substrate;
a first raised source/drain region on the substrate;
a second raised source/drain region on the substrate, wherein the first and second raised source/drain regions are separated by a trench in-between;
a first spacer on a sidewall of the first raised source/drain region;
a second spacer on a sidewall of the second raised source/drain region, wherein the first and second spacers are disposed on the opposite sidewalls of the trench;
a gate structure covering the first and second spacers, the trench and the first and second raised source/drain regions; and
a gate oxide layer located between the gate structure and the first and second raised source/drain regions and between the gate structure and the substrate.
10. The structure of claim 9 , wherein the first spacer consists of a composite oxide/nitride/oxide (ONO) structure.
11. The structure of claim 10 , wherein the composite oxide/nitride/oxide (ONO) structure comprises a tunnel oxide layer of about 40-60 angstroms a silicon nitride layer of about 40-60 angstroms and a top oxide layer of about 40-60 angstroms.
12. The structure of claim 9 , wherein the second spacer consists of a composite oxide/nitride/oxide (ONO) structure.
13. The structure of claim 12 , wherein the composite oxide/nitride/oxide (ONO) structure comprises a tunnel oxide layer of about 40-60 angstroms, a silicon nitride layer of about 40-60 angstroms and a top oxide layer of about 40-60 angstroms.