Hardware architecture for video conferencing
Video processing architectures, systems, and methods for a multipoint control unit are provided. In one example, a video processing system includes a motherboard and at least one daughterboard, each daughterboard having a plurality of processors interconnected via a daughterboard switch, where the daughterboard switch is configured to switch data between the plurality of processors and between the motherboard and daughterboard. The video processing system may further include a plurality of daughterboards each having an identical hardware and/or mechanical configuration. The plurality of daughterboards may be configured to be mechanically and electrically couplable together in any order, and may be stackable to form a series chain of daughterboards extending from the motherboard, each respective daughterboard switch being further configured to switch data to a daughterboard switch on another daughterboard to permit data flow along said series chain.
1. A video processing system for a multipoint control unit, the video processing system comprising:
a motherboard; and
a plurality of daughterboards stacked to form a series chain of daughterboards extending from the motherboard, each daughterboard having a plurality of processors interconnected via a daughterboard switch, the daughterboard switch configured to switch data between the plurality of processors, between the motherboard and each daughterboard, and to a daughterboard switch on another daughterboard to permit data flow along the series chain.
2. The video processing system of claim 1 , wherein the plurality of daughterboards each have an identical hardware configuration.
3. The video processing system of claim 1 , wherein the plurality of daughterboards each have an identical mechanical configuration.
4. The video processing system of claim 1 , wherein the plurality of daughterboards is configured to be mechanically and electrically coupled together in any order.
5. The video processing system of claim 1 , wherein the motherboard comprises a motherboard switch arranged to switch data between the plurality of the daughterboards.
6. The video processing system of claim 5 , wherein the motherboard switch comprises at least part of a field programmable gate array.
7. The video processing system of claim 1 , wherein the daughterboard switch comprises at least part of a field programmable gate array.
8. The video processing system of claim 1 , wherein the plurality of processors comprise digital signal processors.
9. A method for processing video in a multipoint control unit comprising:
receiving data at the multipoint control unit, wherein the multipoint control unit includes a motherboard and a plurality of daughterboards stacked to form a series chain of daughterboards extending from the motherboard, each of the plurality of daughterboards having a plurality of processors interconnected via a daughterboard switch; and
switching the data between the plurality of processors associated with a daughterboard, between the motherboard and the daughterboard, and to a daughterboard switch on another daughterboard to permit data flow along the series chain of daughterboards.
10. The method of claim 9 , wherein the motherboard comprises a motherboard switch configured to switch data between the plurality of daughterboards.
11. A video processing system that transmits a scaled video image to different scaling levels for a multipoint control unit, comprising:
a plurality of processors configured to perform processing of video data;
a plurality of links interconnecting the plurality of processors;
a plurality of stream processors configured to perform video scaling of the video data as it passes between the plurality of processors over the links; and
a memory that stores a network map holding data representative of a network topology, wherein the plurality of stream processors make scaling decisions with reference to the map.
12. The video processing system according to claim 11 , wherein the stream processors form part of a field programmable gate array.
13. The video processing system according to claim 12 , wherein each of the stream processors is associated with a memory co-located on the field programmable gate array.
14. The video processing system according to claim 13 , wherein each of the stream processors has predetermined logic and is also at least partially programmable in operation, by loading one or both of bit masks and data into said memory.
15. The video processing system according to claim 12 , wherein each of the stream processors is associated with a memory that is external to the field programmable gate array.
16. The video processing system according to claim 15 , wherein each of the stream processors has predetermined logic and is also at least partially programmable in operation, by loading one or both of bit masks and data into said memory.
17. The video processing system according to claim 11 , wherein each of the stream processors is configured to perform bandwidth compression on a video stream.
18. The video processing system according to claim 17 , wherein each of the stream processors is associated with a memory and which is configured to store historical information about previous portions of the video stream.
19. The video processing system according to claim 11 , wherein each of the stream processors is arranged to perform bandwidth decompression on a video stream.
20. A method of transmitting a scaled video image to different destinations at different respective scaling levels comprising:
receiving video data at an MCU (multipoint control unit);
processing the video data with a plurality of processors included in the MCU, the plurality of processors being interconnected by a plurality of links;
processing, with a plurality of stream processors included in the MCU, data as it passes between the plurality of processors over the plurality of links;
storing a network map holding data representative of a network topology;
performing, at the MCU, video scaling of the video data in a first of the stream processors to a first scale level required by a first destination and performing subsequent scaling of the video data using a second stream processor to a second, smaller scaling level for a second destination; and
making scaling decisions with reference to the map.
21. A non-transitory computer readable medium encoded with computer program instructions for routing video data, which when executed by a multipoint control unit (MCU) causes the MCU to execute a method comprising:
receiving video data at the MCU;
processing the video data with a plurality of processors included in the MCU, the plurality of processors being interconnected by a plurality of links;
processing, with a plurality of stream processors included in the MCU, data as it passes between the plurality of processors over the plurality of links;
storing a network map holding data representative of a network topology;
performing video scaling of the video data in a first stream processor to a first scale level required by a first destination and performing subsequent scaling of the video data using a second stream processor to a second, smaller scaling level for a second destination; and
making scaling decisions with reference to the map.