Reduced state soft output processing
View Patent ↗Devices, methods, and systems of a communications channel detector are disclosed that can compare a plurality of candidate sequences of bits and decisions to identify unlikely error events. The detector may then discard at least one candidate sequence based on an unlikely error event to produce a set of remaining paths. A branch metric calculator may be adapted to calculate metrics for a set of remaining paths.
1. A detector comprising:
a path generator adapted to produce a plurality of candidate sequences of bits and decisions regarding logic states of detected bits in a signal based on reliability information for the logic states;
a state reducer adapted to:
compare the plurality of candidate sequences of bits and the decisions to identify unlikely error events; and
discard at least one candidate sequence based on an unlikely error event to produce a set of remaining paths; and
a branch metric calculator adapted to calculate metrics for the set of remaining paths.
2. The detector of claim 1 and further comprising:
an add-compare-select unit for selecting one of the remaining paths based on the metrics.
3. The detector of claim 1 wherein the state reducer is further adapted to:
identify likely and unlikely error events based on the comparison of the plurality of sequences of bits and the decisions; and
discard the unlikely error events to produce the set of remaining paths.
4. The detector of claim 3 wherein likely error events are events in the comparison that are separated by at least three bits.
5. The detector of claim 4 wherein likely error events are events in the comparison that are separated by at least five bits.
6. The detector of claim 1 wherein the reliability information is determined using a soft output viterbi algorithm.
7. The detector of claim 1 wherein the detector is part of a communications channel within a data storage device and the detector is configured to detect bits from a data storage medium.
8. A method comprising:
processing in a channel detector circuit comprising:
detecting bits in a signal and generating a plurality of candidate sequences of bits therefrom;
determining reliability information regarding logic states of detected bits in the signal;
generating decisions regarding the logic states based on the reliability information;
comparing the decisions and the plurality of candidate sequences to identify unlikely error events;
discarding at least one of the plurality of candidate sequences based on the unlikely error events to form a set of remaining candidate sequences; and
performing a branch metric calculation on the set of remaining candidate sequences.
9. The method of claim 8 , wherein processing in the channel detector circuit further comprises: selecting a most likely path from the set of remaining candidate sequences based on the branch metric calculation.
10. The method of claim 8 , wherein processing in the channel detector circuit further comprises: identifying likely and unlikely error events based on the comparison of the plurality of sequences of bits and the decisions and discarding the unlikely error events.
11. The method of claim 10 wherein likely error events are events in the comparison that are separated by at least three bits.
12. The method of claim 11 wherein likely error events are events in the comparison that are separated by at least five bits.
13. The method of claim 8 wherein the reliability information is determined using a soft output viterbi algorithm.
14. The method of claim 8 wherein the channel detector circuit is part of a communications channel within a data storage device and the detector is configured to detect bits from a data storage medium.
15. A communications channel, comprising:
a channel medium;
a channel detector adapted to receive a signal from the channel medium, the channel detector comprising:
a path generator adapted to produce a plurality of candidate sequences of bits and decisions regarding logic states of detected bits in the signal based on reliability information for the logic states;
a state reducer adapted to:
compare the plurality of candidate sequences of bits and the decisions to identify unlikely error events;
discard at least one candidate sequence based on an unlikely error event to produce a set of remaining paths; and
a branch metric calculator adapted to calculate metrics for the set of remaining paths.
16. The channel of claim 15 wherein the channel detector further includes an add-compare-select unit for selecting one of the remaining paths as a most likely path based on the metrics.
17. The channel of claim 15 wherein the state reducer is further adapted to:
identify likely and unlikely error events based on the comparison of the plurality of candidate sequences of bits and the decisions; and
discard candidate sequences associated with unlikely error events to produce the set of remaining paths.
18. The channel of claim 17 wherein likely error events are events in the comparison that are separated by at least three bits.
19. The channel of claim 18 wherein likely error events are events in the comparison that are separated by at least five bits.
20. The channel of claim 15 wherein the reliability information is determined using a soft output viterbi algorithm.