On-die termination circuit

1. A termination circuit integrated on a substrate to terminate a transmission line connected from outside the substrate, the termination circuit comprising:

a port to interface with the transmission line;

a first resistive path coupled between the port and a first power supply voltage provided on the substrate, the first resistive path including a first voltage limiter, wherein impedance of the first resistive path is controlled by a first voltage;

a second resistive path coupled between the port and a second power supply voltage provided on the substrate, the second resistive path including a second voltage limiter, wherein impedance of the second resistive path is controlled by a second voltage; and

a calibration circuit to determine the first and second control voltages during a calibration mode.

2. The termination circuit of claim 1 , wherein the first power supply voltage is V cc ; and the second power supply voltage is ground.

3. The termination circuit of claim 1 , wherein the first resistive path and the second resistive path have substantially equal impedance.

4. The termination circuit of claim 3 , wherein the first voltage limiter and the second voltage limiter are to maintain substantially equal and constant voltages when the first and second resistive paths have changing currents.

5. The termination circuit of claim 4 , wherein the first voltage limiter comprises a diode; and the second voltage comprises a diode.

6. The termination circuit of claim 4 , wherein the first voltage limiter comprises a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) biased to maintain a constant voltage; and the second voltage limiter comprises a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) biased to maintain a constant voltage.

7. The termination circuit of claim 6 , wherein the first voltage limiter comprises an n-channel transistor; and the second voltage limiter comprises a p-channel transistor.

8. The termination circuit of claim 6 , further comprising:

an inverter coupled between the first and second voltage limiters to provide an inverted version of a bias signal of the first voltage limiter to the second voltage limiter.

9. The termination circuit of claim 1 , wherein the calibration circuit comprises a third resistive path connected to a fourth resistive path, the third resistive path substantially same as the first resistive path, the fourth resistive path substantially same as the second resistive path.

10. The termination circuit of claim 9 , wherein during the calibration mode,

a known current is connected with the port,

the third and fourth resistive paths are coupled between the first and second power supply voltages, and

a reference voltage is compared with a voltage difference between the port and a connection point between the third and fourth resistive paths to determine the first control voltage.

11. An on-die termination circuit of an integrated circuit, comprising:

a first resistor element, wherein impedance of the first resistor element is adjustable via a control signal;

a second resistor element coupled with the first resistor element, a signal transmission line to be connected to a point between the first and second resistor elements for termination;

a first voltage limiter coupled between the first resistor element and a first power supply voltage of the integrated circuit;

a second voltage limiter coupled between the second resistor element and a second power supply voltage of the integrated circuit; and

a calibration circuit, during a calibration mode the calibration circuit to be coupled to the termination circuit to determine the control signal to calibrate impedance between the first power supply voltage and the point between the first and second resistor elements, during a normal operation mode the calibration circuit to be decoupled from the termination circuit.

12. The termination circuit of claim 11 , wherein the first voltage limiter comprises an NMOS transistor biased to maintain a constant voltage between source and drain; and the second voltage limiter comprises a PMOS transistor biased to maintain a constant voltage between source and drain.

13. The termination circuit of claim 12 , further comprising:

an inverter coupled between a gate of the NMOS transistor and a gate of the PMOS transistor.

14. The termination circuit of claim 13 , wherein the integrated circuit comprises a Complementary Metal Oxide Semiconductor (CMOS).

15. The termination circuit of claim 11 , wherein the calibration circuit comprises a current source selectively coupled to the point between the first and second resistor elements.

16. A device having an integrated circuit formed on a semiconductive substrate, the device comprising:

an input/output (I/O) pin to connect the integrated circuit to a signal transmission line from outside of the device;

a termination circuit coupled with the I/O pin and integrated on the semiconductive substrate, the termination circuit to provide a predetermined termination impedance for the transmission line, the termination circuit including a first resistor, a second resistor and at least one voltage limiter connected in serial between a first power supply voltage and a second power supply voltage, the I/O pin being connected between the first and second resistors; and

a calibration circuit integrated on the semiconductive substrate, the calibration circuit coupled with the termination circuit in a calibration mode and decoupled from the termination circuit during a normal operation mode, the calibration circuit comprising a circuit path to provide a known current through one of the first and second resistors when in the calibration mode, the calibration circuit further comprising a control signal generator to determine a control signal to adjust one of the first and second resistors based on comparing a reference voltage with a voltage change caused by the known current.