Semiconductor device and method of fabricating the same
View Patent ↗A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 formed therein. On the main surface of the semiconductor substrate 101 , there is formed a parallel pn layer having an N-type drift region 104 and P-type column regions 106 alternately arranged therein. In the circumferential region, there is formed a field electrode 120 , but the field electrode 120 is not formed on the P-type column regions 106 . The P-type column regions 106 in the circumferential region are formed with a depth larger than or equal to that of the P-type column regions 106 in the element-forming region.
1. A method of fabricating a semiconductor device comprising:
forming a field electrode on a peripheral region of a first-conductivity-type substrate having formed therein, an element-forming region which has a gate electrode formed therein, and a peripheral region formed in the outer periphery of said element-forming region and having an element-isolating region formed therein;
selectively removing said field electrode; and
forming a parallel pn layer having a first-conductivity-type drift region and second-conductivity-type column regions alternately arranged therein, by implanting a second-conductivity type impurity ion from the main surface of said substrate, in a predetermined region in said element-forming region and below the region from which said field electrode is removed in said peripheral region.
2. The method of fabricating a semiconductor device as claimed in claim 1 , wherein
in said forming said parallel pn layer, said column regions are formed in an island-like manner in said drift region according to a two-dimensional staggered arrangement.
3. The method of fabricating a semiconductor device as claimed in claim 1 , wherein in said selectively removing the field electrode, at least, portions of said field electrode formed on all of said column regions other than those formed in contact with said element-isolating region and those formed in adjacent to said element-isolating region are selectively removed.
4. The method of fabricating a semiconductor device as claimed in claim 1 , further comprising forming a trench surrounding the region, in which said column regions are formed, on the surface of said substrate in said element-forming region;
in said forming a field electrode, a conductive material same as that composing said field electrode is filled in said trench to thereby form a gate electrode in said element-forming region, and said gate electrode and said field electrode are electrically connected; and
in said removing said field electrode, the field electrode on said peripheral region side as viewed from the site of connection between said gate electrode and said field electrode is selectively removed.
5. The method of fabricating a semiconductor device as claimed in claim 1 , wherein
in said forming a parallel pn layer, all of said column regions are formed at the same time.
6. The method of fabricating a semiconductor device as claimed in claim 1 , wherein
in said selectively removing said field electrode, openings are formed in said field electrode.
7. The semiconductor device as claimed in claim 1 , wherein
in said forming a field electrode, said field electrode is formed by forming a polysilicon layer by the CVD process.