Driving method and system for a phase change memory
View Patent ↗An embodiment of a method for driving a phase change memory, comprising counting an access number of a phase change memory, wherein the access number is the number of times that the phase change memory has been accessed; refreshing the phase change memory when the number of times is large than a predetermined number.
1. A method for driving a phase change memory, comprising:
counting an access number of a phase change memory, wherein the access number is the number of times that the phase change memory has been accessed and the access number comprises a combination of a reset number, a set number and a read number; and
refreshing the phase change memory when the access number is large than a predetermined number.
2. The method as claimed in claim 1 , wherein when the set number is larger than the predetermined number, a reset procedure is applied to the phase change memory first, and then a set procedure is applied to the phase change memory.
3. The method as claimed in claim 2 , wherein the reset procedure comprises inputting a reset current to the phase change memory.
4. The method as claimed in claim 2 , wherein the set procedure comprises inputting a set current to the phase change memory.
5. The method as claimed in claim 2 , wherein the data stored in the phase change memory is transmitted and stored in a spare memory before the reset procedure is applied to the phase change memory.
6. The method as claimed in claim 1 , wherein when the phase change memory is refreshed, the access number is set to 0.
7. The method as claimed in claim 1 , wherein the operation of refreshing the phase change memory comprises:
copying and storing the data of the phase change memory to a spare memory;
inputting a reset current to the phase change memory; and
copying and storing the data from the spare memory to the phase change memory.
8. The method as claimed in claim 7 , further comprising inputting a set current to the phase change memory.
9. A driving method for a phase change memory comprising a plurality of memory blocks, comprising:
selecting a memory block;
counting an access number of the selected memory block; and
labeling the selected memory block and refreshing the selected memory block at a specific time when the access number exceeds a predetermined number, wherein the access number comprises a combination of a reset number, a set number and a read number.
10. The method as claimed in claim 9 , wherein when the set number is larger than the predetermined number, a reset procedure is applied to the phase change memory first, and then a set procedure is applied to the phase change memory.
11. The method as claimed in claim 10 , wherein the data of the memory block is stored at another memory block before the selected memory block is refreshed.
12. The method as claimed in claim 9 , further comprising:
setting the access number to zero after the selected memory block is refreshed.
13. The method as claimed in claim 9 , further comprising:
copying and storing the data of the selected memory block to a spare memory block;
inputting a reset current to the phase change memory; and
copying and storing the data from the spare memory block to the selected memory block.
14. The method as claimed in claim 13 , further comprising:
inputting a set current to the selected memory block.
15. The method as claimed in claim 9 , wherein the specific time is the time that the selected memory block is in an idle mode.
16. The method as claimed in claim 9 , wherein the specific time is the time before the data is written to the selected memory block.
17. The method as claimed in claim 9 , wherein the specific time is the time that the selected memory block is activated after a sleeping mode or an off state.
18. A phase change memory writing system, comprising:
a phase change memory;
a spare memory;
a memory controller; and
a counter counting an access number of a phase change memory, wherein the access number is the number of times that the phase change memory has been accessed,
wherein the memory controller is configured to apply a memory refresh procedure to the phase change memory when the access number is larger than a predetermined number, the procedure comprising:
copying and storing the data of the phase change memory to the spare memory;
inputting a reset current to the phase change memory; and
copying and storing the data from the spare memory to the phase change memory.
19. The system as claimed in claim 18 , wherein the phase change memory comprises a plurality of memory blocks.
20. The system as claimed in claim 19 , wherein the spare memory comprises part of the memory blocks.
21. The system as claimed in claim 18 , wherein when the phase change memory is activated, the memory controller refreshes the phase change memory.
22. The system as claimed in claim 18 , wherein the access number is set to zero after the phase change memory is refreshed.