Semiconductor integrated circuit providing for wire bonding directly above an active circuit region, and manufacturing method thereof
View Patent ↗A semiconductor integrated circuit relating to one aspect of the present invention includes a power transistor, at least one or more of first metal patterns functioning as a first electrode of the power transistor and at least one or more of second metal patterns functioning as a second electrode of the power transistor formed in an interlayer insulation film on the transistor, at least one or more of first busses electrically connected to a corresponding first metal pattern of the at least one or more of the first metal patterns, a single second bus electrically connected to the at least one or more of second metal patterns, and a contact pad provided to each of the at least one or more of first busses and the single second bus.
1. A semiconductor integrated circuit comprising:
an integrated power transistor formed on a semiconductor substrate;
an interlayer insulation film formed on the power transistor;
at least one or more of first metal patterns which include a first metal layer formed immediately above the power transistor in the interlayer insulation film and function as a first electrode of the power transistor;
at least one or more of second metal patterns which include the first metal layer and function as a second electrode of the power transistor;
a plurality of first busses which include a second metal layer formed immediately above the first metal layer in the interlayer insulation film and are electrically connected to a corresponding first metal pattern among at least one or more of first metal patterns, each of said plurality of first busses are separated from each other by another interlayer insulation film;
a single second bus which includes the second metal layer and is electrically connected to the at least one or more of second metal patterns; and
contact pads formed on each of said plurality of first busses and on the single second bus.
2. The semiconductor integrated circuit according to claim 1 , wherein at least one or more of contact pads are provided to the single second bus.
3. The semiconductor integrated circuit according to claim 1 , wherein:
a plurality of power transistors are disposed at a corner part of the semiconductor integrated circuit chip; and
each of contact pads disposed immediately above at least one or more of the power transistors is connected to a corresponding lead frame via a connecting member.
4. The semiconductor integrated circuit according to claim 1 , wherein each of the first busses has a different surface area.
5. The semiconductor integrated circuit according to claim 1 , wherein each of the first busses has the same surface area.
6. The semiconductor integrated circuit according to claim 1 , wherein the power transistor is divided into a plurality of members by a separating layer so as to correspond to each of the first busses.
7. The semiconductor integrated circuit according to claim 1 , wherein the size in plan view of the power transistor is more than the size of each of the contact pads.
8. The semiconductor integrated circuit according to claim 7 , wherein each of the contact pads is, in plan view, included in a region where the power transistor is formed.
9. The semiconductor integrated circuit according to claim 7 , wherein some of the contact pads are, in plan view, protruded in part from a region where the power transistor is formed.
10. The semiconductor integrated circuit according to claim 7 , wherein some of the contact pads are, in plan view, protruded entirely from a region where the power transistor is formed.
11. The semiconductor integrated circuit according to claim 1 , wherein an area of an upper surface of the second bus is substantially equal to an area defined by the totality of areas of upper surfaces of said plurality of first busses.