Method of forming pre-metal dielectric layer of semiconductor device
View Patent ↗A method of forming a pre-metal dielectric (PMD) layer of a semiconductor device using a chemical mechanical polishing (CMP) process which can be suitable for easily recognizing an alignment key. Such a method can reduce or otherwise eliminate alignment key erosion due to CMP by previously forming an alignment key pattern of polysilicon in an active region of a semiconductor scribe lane.
1. A method comprising:
providing a semiconductor substrate having a semiconductor device;
forming an etch-stop layer over the semiconductor substrate;
forming a plurality of alignment key patterns composed of polysilicon over the etch-stop layer in an active region of a scribe lane of the semiconductor substrate;
forming a first PMD layer over the semiconductor substrate including the etch-stop layer and the alignment key patterns;
forming a second PMD layer over the semiconductor substrate including the first PMD layer; and then
forming a plurality of contacts against sidewalls of the plurality of alignment patterns.
2. The method of claim 1 , wherein forming the etch-stop layer comprises:
depositing a SiN layer having a thickness of between 300 to 500Åover the semiconductor substrate.
3. The method of claim 1 , wherein forming the first PMD layer comprises:
depositing a TEOS oxide layer having a thickness of between over the semiconductor substrate including the first PMD layer.
4. The method of claim 1 , wherein the plurality of alignment key patterns have a removal rate lower than the removal rates of the first PMD layer and the second PMD layer.
5. A method comprising: forming at least one STI-type isolation layer in a semiconductor substrate; and forming an alignment key pattern in the STI isolation layer, wherein forming the alignment key pattern comprises:
forming an etch-stop layer over the semiconductor substrate including the at least one STI isolation layer;
forming an insulating layer over the semiconductor substrate including the etch-stop layer;
forming an oxide layer over the first insulating layer;
forming a plurality of contact holes in the at least one STI isolation layer; and then
forming a contact in each of the plurality of contact holes.
6. The method of claim 5 , wherein the etch-stop layer comprises SiN.
7. The method of claim 6 , wherein the etch-stop layer has a thickness of between 300 to 500Å.
8. The method of claim 5 , wherein the insulating layer has a thickness of approximately 7000Åor more.
9. The method of claim 8 , wherein the insulating layer comprises a pre-metal dielectric material.
10. The method of claim 9 , wherein the pre-metal dielectric material comprises at least one of O 3 -TEOS oxide, BPSG insulating material and HDP CVD oxide.
11. The method of claim 5 , wherein the oxide layer comprises a pre-metal dielectric material.
12. The method of claim 11 , wherein the pre-metal dielectric material comprises a TEOS oxide.
13. The method of claim 6 , wherein forming the plurality of contact holes comprises performing a dry etch on the etch-stop layer, the insulating layer and the oxide layer.
14. The method of claim 5 , wherein forming the contacts comprises gap-filling a conductive layer in each one of the plurality of contact holes.
15. The method of claim 14 , wherein the conductive layer comprises a polysilicon material doped with an impurity of a metal.
16. The method of claim 15 , wherein the polysilicon material is doped with the impurity of tungsten.