Ion implantation method for high voltage device

1. An ion implantation method for forming a high-voltage device, the method comprising:

defining a logic region and a high-voltage region in a semiconductor substrate;

forming a first conductive well region in the logic region;

forming a second conductive well region in the high-voltage region;

forming a first gate insulation layer on the semiconductor substrate in the logic region and a second gate insulation layer on the semiconductor substrate in the high-voltage region, the second gate insulation layer being thicker than the first gate insulation layer;

forming a mask pattern which exposes the first conductive well region in the logic region and the second conductive well region in the high-voltage region;

simultaneously forming a hollow region in the logic region, and a source region in the high-voltage region, by simultaneously implanting first conductive impurities into the logic region and source region of the semiconductor substrate using the mask pattern as an ion implantation mask; and

forming a second conductive impurity layer in the hollow region by implanting second conductive impurities into the logic region and the source region in the high-voltage region using the mask pattern as an ion implantation mask, wherein the second gate insulation layer prevents the implantation of ions in the source regions of the semiconductor substrate.

2. The method according to claim 1 , wherein the second gate insulation layer in the high-voltage region of the semiconductor substrate confines the implantation of the second conductive impurities to the logic region of the semiconductor substrate.

3. The method according to claim 1 ,

wherein the hollow region is formed in the first conductive well region, and the source region is formed in the second conductive well region.

4. The method according to claim 1 , wherein the second conductive impurities are projected to a depth that is smaller than the thickness of the second gate insulation layer.

5. The method according to claim 1 , wherein the depth of the second conductive impurity layer is smaller than the depth of the hollow region.

6. The method according to claim 5 , wherein the second conductive impurity layer is formed in the hollow region of the logic region.

7. The method according to claim 1 , wherein:

the hollow region in a logic N-type metal oxide semiconductor NMOS transistor and the source region in a high-voltage P-type metal oxide semiconductor (PMOS) transistor are simultaneously formed simultaneously using a first ion implantation mask; and

the hollow region in a logic PMOS transistor and the source region in a high-voltage NMOS transistor are simultaneously formed using a second ion implantation mask.

8. The method according to claim 7 , further comprising:

forming a N-diffusion region in the logic NMOS transistor using the first ion implantation mask; and

forming a P-diffusion region in the logic PMOS transistor using the second ion implantation mask,

wherein the second gate insulation layer prevents the implantation of ions in the source regions in the high-voltage PMOS transistor and high-voltage NMOS transistor of the semiconductor substrate.

9. An ion implantation method for forming a high-voltage device, the method comprising:

defining a logic region and a high-voltage region in a semiconductor substrate;

forming a first conductive well region in the logic region;

forming a second conductive well region in the high-voltage region;

forming a first gate insulation layer on the semiconductor substrate in the logic region and a second gate insulation layer on the semiconductor substrate in the high-voltage region, the second gate insulation layer being thicker than the first gate insulation layer;

forming mask pattern which exposes the first conductive well region in the logic region and the second conductive well region in the high-voltage region;

simultaneously forming a hollow region comprising a N-type metal oxide semiconductor NMOS transistor in the logic region, and a source region comprising a P-type metal oxide semiconductor (PMOS) transistor in the high-voltage region, by simultaneously implanting first conductive impurities into the logic region and source region of the semiconductor substrate using the mask pattern as an ion implantation mask; and

forming a second conductive impurity layer in the hollow region of the logic region by implanting second conductive impurities into the logic region and the source region in the high-voltage region using the mask pattern as an ion implantation mask, wherein the second gate insulation layer prevents the implantation of ions in the source regions of the semiconductor substrate.

10. The method according to claim 9 , wherein the second gate insulation layer in the high-voltage region of the semiconductor substrate confines the implantation of the second conductive impurities to the logic region of the semiconductor substrate.

11. The method according to claim 9 ,

wherein the hollow region is formed in the first conductive well region, and the source region is formed in the second conductive well region.

12. The method according to claim 9 , wherein the second conductive impurities are projected to a depth that is smaller than the thickness of the second gate insulation layer.

13. The method according to claim 9 , wherein the depth of the second conductive impurity layer is smaller than the depth of the hollow region.

14. The method according to claim 9 , further comprising:

forming a N-diffusion region in the logic NMOS transistor using the first ion implantation mask; and

forming a P-diffusion region in the logic PMOS transistor using the second ion implantation mask,

wherein the second gate insulation layer prevents the implantation of ions in the source regions in the high-voltage PMOS transistor and high-voltage NMOS transistor of the semiconductor substrate.