Adjusting program and erase voltages in a memory device
A method and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. A method includes applying a first voltage level to a first edge word line of a memory block string and applying a second voltage level to a second edge word line of the memory block string. The method might also include applying a third voltage level to non-edge word lines of the memory block string.
1. A method of erasing memory cells comprising:
applying a first voltage level to a control gate of a first edge memory cell of a string;
applying a second voltage level to a control gate of a second edge memory cell of the string; and
applying a third voltage level to a control gate of at least one non-edge memory cell of the string.
2. The method of claim 1 , wherein the third voltage level is greater than the first and second voltage levels.
3. The method of claim 1 , wherein the first voltage level is approximately 0 volts, and the second and third voltage levels are each between approximately 0.5 volts and 2.5 volts.
4. The method of claim 1 , wherein the first and second voltage levels are determined based upon the distance between the control gates of the first edge memory cell and the second edge memory cell to select gates of the string.
5. The method of claim 1 , wherein the first edge memory cell and the second edge memory cell of the string are part of a first block in a pair of blocks, wherein the first edge memory cell is adjacent to a source select gate of the first block and the second edge memory cell is adjacent to a drain select gate of the first block.
6. The method of claim 5 , wherein applying the first voltage level to the control gate of the first edge memory cell comprises applying the first voltage level to a control gate of a first edge memory cell of a second block in the pair of blocks, and wherein applying the second voltage level to the control gate of the second edge memory cell comprises applying the second voltage level to a control gate of a second e memory cell of the second block.
7. The method of claim 6 , wherein the first edge memory cell of the second block is adjacent to a drain select gate of the second block and the second edge memory cell of the second block is adjacent to a source select gate of the odd block string.
8. A method of operating a memory array comprising:
applying a first program voltage to a control gate of a first memory cell adjacent to a select gate of a first block of memory cells of a pair of blocks and applying a second program voltage to a control gate of a memory cell adjacent to a select gate of a second block of memory cells of the pair of blocks, wherein the first program voltage is greater than or equal to the second program voltage.
9. The method of claim 8 , comprising applying a third program voltage to a control gate of an other memory cell of the first block, wherein the other memory cell of the first block is adjacent to an other select gate of the first block, and wherein the third voltage is less than the first voltage level.
10. The method of claim 9 , comprising applying a fourth program voltage to a control gate of an other memory cell of the second block, wherein the other memory cell of the second block is adjacent to an other select gate of the second block, and wherein the fourth voltage is less than or equal to the third program voltage.
11. A method for configuring a memory array comprising:
determining a plurality of voltage levels to apply to control gates of the memory array;
setting the voltages levels to be applied to the control gates; and
determining if the memory cells in the memory array are misaligned using data gathered from a sense block.
12. The method of claim 11 , wherein determining voltage levels to apply to control gates comprises using data gathered from a sense block.
13. The method of claim 11 , wherein determining the voltage levels to apply to the control gates comprises retrieving data from a memory location.
14. The method of claim 11 , wherein setting the voltage levels comprises setting voltages for the word lines of first and second blocks of a pair of blocks of a NAND array.
15. The method of claim 11 , wherein the voltages are program voltages for programming the memory cells of the memory array and they are set according to the following pattern: (V pg for even WL( 0 )≧V pg for odd WL(M))>(V pg for odd WL( 0 )≧V pg for even WL(M)).
16. The method of claim 11 , wherein the voltages are program voltages for programming the memory cells of the memory array and they are set according to the following: (V pg for odd block WL( 0 )≧V pg for even block WL(M))>(V pg even WL( 0 )≧V pg for odd block WL(M)).