Semiconductor device, wafer and method of designing and manufacturing the same
View Patent ↗A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interconnect) is disposed in a same orientation such that the longitudinal direction of the interconnects is aligned with a scanning direction of a scanning type exposure equipment, in an interconnect layer that includes a narrowest interconnect or a narrowest spacing between the interconnects. Aligning thus the direction of the vibration with the longitudinal direction of the pattern can minimize the positional deviation due to the vibration.
1. A method of manufacturing a semiconductor device comprising a plurality of circuit blocks in which a plurality of P-MOS transistors and N-MOS transistors is alternately disposed, comprising:
performing an exposure, with a longitudinal direction of a frequently used interconnect aligned with a scanning direction for a wafer stage and a reticle stage of an exposure equipment to be employed for fabricating said semiconductor device, in a first interconnect layer that includes a narrowest interconnect or a narrowest spacing between interconnects among interconnect layers connecting said P-MOS transistors and said N-MOS transistors in at least one of said circuit blocks.
2. The method according to claim 1 , wherein a width of said interconnect or a spacing between said interconnects orthogonal to said frequently used interconnect in said first interconnect layer is wider than a width of said frequently used interconnect or a spacing between said frequently used interconnect.
3. The method according to claim 1 , wherein a minimum width of said frequently used interconnect is not wider than 0.15 μm, and minimum spacing between said frequently used interconnects is not wider than 0.15 μm.
4. The method according to claim 1 , wherein said minimum spacing between said frequently used interconnects is not more than 0.3 μm.
5. A method of manufacturing a semiconductor device comprising a plurality of chips provided on a semiconductor substrate; and a plurality of interconnect layers respectively provided on said chips via an insulating layer, comprising:
performing an exposure, with a longitudinal direction of a frequently used interconnect aligned with a scanning direction for a wafer stage and a reticle stage of an exposure equipment to be employed for the exposure, to form a first interconnect layer that includes a narrowest interconnect or a narrowest spacing between interconnects among the plurality of the insulating layers.
6. The method according to claim 5 , wherein a width of said interconnect or a spacing between said interconnects orthogonal to said frequently used interconnect in said first interconnect layer is wider than a width of said frequently used interconnect or a spacing between said frequently used interconnect.
7. The method according to claim 5 , wherein a minimum width of said frequently used interconnect is not wider than 0.15 μm, and minimum spacing between said frequently used interconnects is not wider than 0.15 μm.
8. The method according to claim 5 , wherein said minimum spacing between said frequently used interconnects is not more than 0.3 μm.
9. A method of manufacturing a semiconductor device comprising a plurality of chips provided on a semiconductor substrate; a first interconnect layer respectively provided on said chips via an insulating layer so as to connect said chips; a second interconnect layer provided on said first interconnect layer via an insulating layer so as to connect said first interconnect layers; and a third interconnect layer provided on said second interconnect layer via an insulating layer so as to connect said second interconnect layers, comprising:
performing an exposure, with a longitudinal direction of a frequently used interconnect aligned with a scanning direction for a wafer stage and a reticle stage of an exposure equipment to be employed for the exposure, to form the first interconnect layer.
10. The method according to claim 9 , wherein a width of said interconnect or a spacing between said interconnects orthogonal to said frequently used interconnect in said first interconnect layer is wider than a width of said frequently used interconnect or a spacing between said frequently used interconnect.
11. The method according to claim 9 , wherein a minimum width of said frequently used interconnect is not wider than 0.15 μm, and minimum spacing between said frequently used interconnects is not wider than 0.15 μm.
12. The method according to claim 9 , wherein said minimum spacing between said frequently used interconnects is not more than 0.3 μm.
13. A method of manufacturing a semiconductor device comprising a logic unit including two or more logic blocks in which a plurality of basic cells constituted of a pair of a P-MOS transistor and an N-MOS transistor is regularly aligned, such that said basic cells are of a uniform size in the respective logic blocks; and a first interconnect layer that includes a narrowest interconnect or a narrowest spacing between interconnects among said plurality of interconnect layers connecting said basic cells in at least one of said logic blocks, comprising:
performing an exposure, with a longitudinal direction of a frequently used interconnect aligned with a scanning direction for a wafer stage and a reticle stage of an exposure equipment to be employed for the exposure, to form the first interconnect layer.
14. The method according to claim 13 , wherein, in said logic block in which a cell height of said basic cells is shorter than a spacing between power supply lines in a second interconnect layer provided on said first interconnect layer via an insulating layer, a longitudinal direction of said frequently used interconnect in said first interconnect layer is orthogonal to the cell height direction.
15. The method according to claim 13 , wherein, in said logic block in which a cell height of said basic cells is longer than said spacing between power supply lines in said second interconnect layer provided on said first interconnect layer via said insulating layer, a longitudinal direction of said frequently used interconnect in said first interconnect layer is parallel to the cell height direction.
16. The method according to claim 13 , wherein a width of said interconnect or a spacing between said interconnects orthogonal to said frequently used interconnect in said first interconnect layer is wider than a width of said frequently used interconnect or a spacing between said frequently used interconnect.
17. The method according to claim 13 , wherein a minimum width of said frequently used interconnect is not wider than 0.15 μm, and minimum spacing between said frequently used interconnects is not wider than 0.15 μm.
18. The method according to claim 13 , wherein said minimum spacing between said frequently used interconnects is not more than 0.3 μm.