LDMOS with channel stress
View Patent ↗A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device. During a portion of forming the remainder of the MOS device, dopant of the first conductivity type of the first doped region of the active area and dopant of the second conductivity type of the second doped region of the active area diffuses into overlying portions of the strained semiconductor layer to create a correspondingly doped strained semiconductor layer, thereby providing corresponding doping for the biaxially strained channel.
1. A method of forming a metal oxide semiconductor (MOS) device comprising:
defining an active area in an unstrained semiconductor layer structure, the active area including at least a first doped region of a first conductivity type and a second doped region of a second conductivity type;
depositing a hard mask overlying the active area and a region outside of the active area;
patterning the hard mask to expose the active area;
selectively growing a strained semiconductor layer overlying the exposed active area, the strained semiconductor layer thereby providing a biaxially strained channel for the MOS device; and
forming a remainder of the MOS device including forming at least a gate dielectric, gate electrodes, source and drain implants, and sidewall spacers, wherein during a portion of forming the remainder of the MOS device, dopant of the first conductivity type of the first doped region of the active area and dopant of the second conductivity type of the second doped region of the active area diffuses into overlying portions of the strained semiconductor layer to create a correspondingly doped strained semiconductor layer, the correspondingly doped strained semiconductor layer thereby providing corresponding doping for the biaxially strained channel of the MOS device.
2. The method of claim 1 , wherein the MOS device comprises a laterally diffused metal oxide semiconductor (LDMOS) transistor.
3. The method of claim 1 , wherein the hard mask comprises an undoped oxide.
4. The method of claim 3 , further wherein the undoped oxide comprises a CVD oxide having a thickness on the order of 400 angstroms.
5. The method of claim 1 , wherein a portion of the hard mask overlying the region outside of the active area provides protection to corresponding underlying portions of the semiconductor layer structure from subsequent MOS device processing.
6. The method of claim 1 , wherein the strained semiconductor layer is undoped.
7. The method of claim 1 , wherein the strained semiconductor layer has a thickness on the order of 100 to 300 angstroms.
8. The method of claim 1 , wherein the strained semiconductor layer includes at least one selected from the group consisting of a SiC strained layer and a SiGe strained layer.
9. The method of claim 8 , wherein the SiC strained layer comprises tensile strained SiC for an n-type MOS device.
10. The method of claim 9 , further wherein the SiC strained layer comprises on the order of one-tenth to two atomic percent (0.1 to 2 at. %) carbon.
11. The method of claim 9 , further wherein the n-type MOS device comprises an n-type LDMOS device.
12. The method of claim 8 , wherein the SiGe strained layer comprises compressive strained SiGe for a p-type MOS device.
13. The method of claim 12 , further wherein the p-type MOS device comprises a p-type LDMOS device.
14. The method of claim 12 , further wherein the SiGe strained layer comprises on the order of ten to fifty atomic percent (10 to 50 at. %) germanium.
15. The method of claim 1 , further comprising:
prior to forming the remainder of the MOS device, capping the strained semiconductor layer with a selectively grown semiconductor material.
16. The method of claim 15 , wherein the selectively grown semiconductor material provides a consumable layer for consumption during the forming of at least one gate dielectric.
17. The method of claim 16 , further wherein the selectively grown semiconductor material comprises epitaxial silicon.
18. The method of claim 16 , wherein the selectively grown semiconductor material has a thickness on the order of 50 to 150 angstroms.
19. A method of forming a metal oxide semiconductor (MOS) device comprising:
defining an active area in an unstrained semiconductor layer structure, the active area including at least a first doped region of a first conductivity type and a second doped region of a second conductivity type;
depositing a hard mask overlying the active area and a region outside of the active area;
patterning the hard mask to expose the active area;
selectively growing a strained semiconductor layer overlying the exposed active area, the strained semiconductor layer thereby providing a biaxially strained channel for the MOS device, wherein the strained semiconductor layer includes at least one selected from the group consisting of a SiC strained layer and a SiGe strained layer, further wherein the SiC strained layer comprises on the order of one-tenth to two atomic percent (0.1 to 2 at. %) carbon, further wherein the SiGe strained layer comprises on the order of ten to fifty atomic percent (10 to 50 at. %) germanium;
capping the strained semiconductor layer with a selectively grown semiconductor material; and
forming a remainder of the MOS device including forming at least a gate dielectric, gate electrodes, source and drain implants, and sidewall spacers, wherein during a portion of forming the remainder of the MOS device, dopant of the first conductivity type of the first doped region of the active area and dopant of the second conductivity type of the second doped region of the active area diffuses into overlying portions of the strained semiconductor layer to create a correspondingly doped strained semiconductor layer, the correspondingly doped strained semiconductor layer thereby providing corresponding doping for the biaxially strained channel of the MOS device.