IP Library › Granted Patent US 7,633,813
Granted Patent B2
US 7,633,813 · App. 11/951,936 · Granted Dec 15, 2009

Method of performing an erase operation in a non-volatile memory device

Assignee: Hynix Semiconductor Inc.
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Quick Facts
Patent No.
US 7,633,813
App. No.
11/951,936
Granted
Dec 15, 2009
Kind
B2
Abstract

An erase method of a memory cell array which includes at least one block having MLC is disclosed. The erase method includes shifting every threshold voltage distribution into a threshold voltage distribution having a highest level by pre-programming every cell in a block selected for erase, performing an erase operation on the pre-programmed memory block, performing a soft program and a verifying operation on the memory block, dividing the memory block into a first group and a second group when the memory block is passed, performing a verifying operation on the first group and performing a soft program and a verifying operation on the first group when the first group is not passed, and performing a verifying operation on the second group when the first group is passed and performing a soft program and a verifying operation on the second group when the second group is not passed.

Claims (67)

1. A method of performing an erase operation in a non-volatile memory device having a memory cell array which includes at least one blocks having multi level cells, the method comprising:

shifting every threshold voltage distribution into a threshold voltage distribution having highest level by pre-programming every cell in a block selected for erase;

performing an erase operation on the pre-programmed memory block;

performing a soft program and a verifying operation on the memory block;

dividing the memory block into a first group and a second group in case that the memory block is passed in accordance with the verifying result;

performing a verifying operation on the first group, and performing a soft program and a verifying operation on the first group in case that the first group is not passed; and

performing a verifying operation on the second group in case that the first group is passed, and performing a soft program and a verifying operation on the second group in case that the second group is not passed in accordance with the verifying result.

2. The method of claim 1 , wherein the step of verifying the first group or the second group is substantially identical to the step of verifying the soft program.

3. The method of claim 1 , wherein the step of preprogramming includes:

applying a program voltage to every word line in the selected block;

applying a power supply voltage to a drain select line in the selected block;

applying a voltage of 0V to a source select line in the selected block; and

programming the selected block.

4. The method of claim 1 , wherein the step of performing the erase operation includes:

applying a voltage of 0V to a word line in the selected block;

changing a drain select line and a source select line in the selected block into floating state; and

performing the erase operation by applying a high voltage to a substrate (or well).

5. The method of claim 1 , wherein the step of performing the soft program includes:

applying a program voltage to a word line selected for the soft program in the selected block;

applying a pass voltage to a word line not selected; and

applying a power supply voltage to a drain select line in the selected block, providing a voltage of 0V to a source select line, and performing the soft program.

6. The method of claim 1 , wherein the step of performing the verifying operation after the soft program includes:

applying a voltage of 0V to a selected word line in the selected block, wherein the soft program is performed on the selected word line;

applying a pass voltage to a word line not selected; and

applying a power supply voltage to a drain select line and a source select line in the selected block, and performing the verifying operation.

7. The method of claim 1 , further comprising:

dividing the first group and the second group into low rank groups; and

performing a verifying operation on one of the low rank groups, performing a soft program and a verifying operation on the low rank group in case that the low rank group is not passed, and performing a verifying operation, a soft program and a verifying operation on the other low rank group in case that the low rank group is passed.

8. A method of performing an erase operation in a non-volatile memory device having a memory cell array which includes at least one blocks having multi level cells, the method comprising:

shifting every threshold voltage distribution into a threshold voltage distribution having highest level by pre-programming every cell in a block selected for erase;

performing an erase operation on the pre-programmed memory block;

performing a soft program and a verifying operation on the memory block;

dividing the memory block into a first group and a second group in case that the memory block is passed in accordance with the verifying result;

performing a verifying operation on the first group and the second group, and indicating a flag to a group not passed; and

performing a soft program and a verifying operation on the group to which the flag is indicated.

9. The method of claim 8 , wherein the step of verifying the first group and the second group is substantially identical to the step of verifying the soft program.

10. The method of claim 8 , wherein the step of preprogramming includes:

applying a program voltage to every word line in the selected block;

applying a power supply voltage to a drain select line in the selected block;

applying a voltage of 0V to a source select line in the selected block; and

programming the selected block.

11. The method of claim 8 , wherein the step of performing the erase operation includes:

applying a voltage of 0V to a word line in the selected block;

changing a drain select line and a source select line in the selected block into floating state; and

performing the erase operation by applying a high voltage to a substrate (or well).

12. The method of claim 8 , wherein the step of performing the soft program includes:

applying a program voltage to a word line in the group to which the flag is indicated;

applying a pass voltage to a word line in the group to which the flag is not indicated; and

applying a power supply voltage to a drain select line in the selected block, providing a voltage of 0V to a source select line, and performing the soft program.

13. The method of claim 8 , wherein the step of performing the verifying operation after the soft program includes:

applying a voltage of 0V to a word line in a group to which the flag is indicated;

applying a pass voltage to a word line in the group to which the flag is not indicated; and

applying a power supply voltage to a drain select line and a source select line in the selected block, and performing the verifying operation.

14. The method of claim 8 , further comprising:

dividing the first group and the second group into low rank groups;

performing in sequence a verifying operation on the low rank groups, and indicating a flag to the group not passed; and

performing a soft program and a verifying operation on the group to which the flag is indicated.

15. The method of claim 14 , further comprising:

removing the flag indication of the group passed in accordance with the verifying result on the soft program.

16. A method of performing an erase operation in a nonvolatile memory device, the method comprising:

performing an erase operation on an area of the memory device;

performing a first soft program operation on the area of the memory device;

dividing the area of the memory device into a first group and second group; and

performing a second soft program operation on the first group and a third soft program operation on the second group.

17. The method of claim 16 , wherein the soft program operation includes:

applying a program voltage to a selected word line; and

applying a verify voltage to the selected word line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2008
From: WANG, JONG HYUN; PARK, SE CHUN; PARK, SEONG HUN
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 020452/0602 →
Priority Claims (2)
KR 10-2007-0007042 · Jan 23, 2007 · national
KR 10-2007-0079477 · Aug 8, 2007 · national
Continuity (1)
Related Publication 20080175069A1 · Jul 24, 2008