INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS
An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.
1 . An integrated circuit system comprising:
providing a PFET device including a doped epitaxial layer; and
forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.
2 . The system as claimed in claim 1 wherein:
providing the PFET device including the doped epitaxial layer includes forming the doped epitaxial layer from silicon germanium.
3 . The system as claimed in claim 1 wherein:
providing the PFET device including the doped epitaxial layer includes forming the doped epitaxial layer from silicon.
4 . The system as claimed in claim 1 wherein:
forming the source/drain extension by employing the energy source to diffuse a dopant includes diffusing boron.
5 . The system as claimed in claim 1 wherein:
forming the source/drain extension by employing the energy source to diffuse a dopant includes a millisecond anneal.
6 . An integrated circuit system comprising:
providing a substrate including an NFET device, a PFET device and an isolation structure;
forming an insulation layer over the integrated circuit system;
etching the insulation layer to form a PFET gate sidewall spacer adjacent a PFET gate;
etching the substrate to form a recess;
forming a doped epitaxial layer within the recess; and
annealing the doped epitaxial layer to form a source/drain extension.
7 . The system as claimed in claim 6 wherein:
etching the substrate to form the recess includes forming the recess aligned to the PFET gate sidewall spacer.
8 . The system as claimed in claim 6 wherein:
forming the doped epitaxial layer within the recess includes forming a boron doped epitaxial silicon-germanium layer or a boron doped epitaxial silicon layer.
9 . The system as claimed in claim 6 wherein:
annealing the doped epitaxial layer to form the source/drain extension includes a millisecond anneal or a rapid thermal anneal followed by a millisecond anneal.
10 . The system as claimed in claim 6 further comprising:
forming an electrical contact over an NFET source/drain, an NFET gate, the doped epitaxial layer, and the PFET gate.
11 . An integrated circuit system comprising:
a PFET device including a doped epitaxial layer; and
a diffused source/drain extension adjacent the doped epitaxial layer.
12 . The system as claimed in claim 11 wherein:
the doped epitaxial layer includes silicon-germanium.
13 . The system as claimed in claim 11 wherein:
the doped epitaxial layer includes silicon.
14 . The system as claimed in claim 11 wherein:
the doped epitaxial layer includes a p-type dopant.
15 . The system as claimed in claim 11 wherein:
the doped epitaxial layer includes boron.
16 . The system as claimed in claim 11 wherein:
the doped epitaxial layer is offset from a PFET gate by a width dimension of PFET gate sidewall spacer.
17 . The system as claimed in claim 11 wherein:
the doped epitaxial layer is within a recess.
18 . The system as claimed in claim 11 wherein:
the diffused source/drain extension is between the doped epitaxial layer and a PFET gate.
19 . The system as claimed in claim 11 wherein:
the diffused source/drain extension overlaps with a PFET gate edge.
20 . The system as claimed in claim 11 wherein:
the PFET device is part of a CMOS configuration.